Mitel MT90840 Functional Description, Device Operation, Time Slot Interchange Operation Switching

MT90840 Preliminary Information

Functional Description

The MT90840 Distributed Hyperchannel Switch is a large switching, multiplexing, and rate-adapting device. The MT90840 bridges serial-bus telecom components, using the Mitel ST-BUS or other industry-standard serial buses, onto a higher speed “backbone”. Mixed data, voice and video signals can be time-interchanged or multiplexed from serial Time Division Multiplexed (TDM) streams onto a high speed parallel bus. The parallel bus can be used for interconnect, or an external framer can be connected to the parallel bus to access serial isochronous backbones operating at up to 155 Mbps SONET rates (STS-3).

The MT90840 Distributed Hyperchannel Switch supports real-time multimedia applications through constant delay switching. Multimedia data at N x 64 kbps rates uses N bytes (“time slots”, or “channels”) per 125 μsec frame. This is also referred to as hyperchannel data. To ensure the integrity of data at N x 64 kbps rates, the network must ensure that the N bytes in a given input frame remain together as a frame, and arrive at the destination as a frame. The MT90840 supports this requirement by providing constant delay (frame integrity) which ensures that the multiple time slots of associated data remain in the intended order.

Total TDM channel capacity of the MT90840 at maximum data rates is:

•512 serial input time slots,

•512 serial output time slots,

•2430 parallel input time slots, and

•2430 parallel output time slots.

The number of time slots available is dependent upon the selected data rates, and is reduced at lower data rates.

Figure 1 shows the MT90840 functional block diagram. The figure shows the TDM data paths and the device interfaces.

The MT90840 has three main TDM data paths:

•Transmit Path: serial port input (STi) to parallel port output (PDo),

•Receive Path: parallel port input (PDi) to serial port output (STo),

•Bypass and Parallel-Switching: PDi to PDo.

In addition, Mitel Message Mode capabilities allow the user to force data on TDM output time slots and to monitor TDM input time slots through the microprocessor port.

The MT90840 has four main interfaces:

•the serial TDM bus interface (STi, STo and timing),

•the parallel TDM bus interface (PDi, PDo and timing) with programmable control outputs (CTo),

•the microprocessor (CPU) interface,

•the test interface (JTAG).

The MT90840 supports four major timing/switching modes:

•TM1/Ring Master: PDo timing slaved to STi/o timing, PDi timing elastic;

•TM2/Ring Slave: PDo and STi/o timing slaved to PDi;

•TM3/Bus Slave: PDo and PDi timing tied together, STi/o timing slaved to parallel bus;

•TM4/Parallel Switching: parallel channel switching from PDi to PDo.

Other features of the MT90840 are programmable for individual TDM channels on the serial and parallel ports (per-channel features):

•Mitel Message Mode,

•Per-channel output enable,

•Per-channel bypass (parallel bus),

•Programmable CTo control outputs (parallel bus),

•Per-channel direction control (serial bus).

Device Operation

Time Slot Interchange Operation (Switching)

The MT90840 provides access and time slot interchange (switching) functions between the serial and parallel TDM data ports. Switching is provided on three paths: transmit (serial input to parallel output), receive (parallel input to serial output) and bypass/parallel-switching (parallel input to parallel output). Switching functions between serial data streams are not provided.

The MT90840 guarantees wideband or hyper-channel data integrity through the switch by using constant delay switching. This is done by storing a full frame (125 μsec) of data at the input rate and then, under control of the Connection Memory for that path, reading the frame at the output data rate (frame integrity). Therefore the Transmit Path and the Receive Path each have separate Data and Connection Memories.

Switching in a given data path is controlled by programming the Connection Memory for that path. Each output time slot has a control-address in the path’s Connection Memory. Each input time slot has

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