Manuals / Mitel / Personal Care / Pacemaker

Mitel MT90840 manual Serial Port with Negative Polarity F0 ST-BUS

Models: MT90840

1 50

Download 50 pages 39.17 Kb

Page 35

Image 35

Preliminary Information

MT90840

Foi input (8 kHz)

C4/8R1 (4.096 MHz)

STi0-7

STo0-7

tfrw

	tfrs	tfrh
		tclk
tT	tclkh	tclkl
	bit 0, ch. 31
		tsod

bit 0, ch. 31



	tstis			tstih

bit 7, ch. 0

Serial Port with Negative Polarity F0 (ST-BUS)

C4/8R1 (4.096 MHz)

STo0-7

STi0-7

F0i input (8 kHz)

		tclk
tt	tclkh	tclkl
	tsod
bit 0, ch. 31		bit 7, ch. 0	bit 6, ch. 0
		tstis	tstih
bit 0, ch. 31			bit 7, ch. 0
	tfrs	tfrh
		tfrw

Serial Port with Positive Polarity F0 (GCI)

Note: In TM2 with SFDI=1, C4/8R1 may have reversed polarity from that shown.

Figure 18 - Serial Port Timing for 2.048 Mbps Operation - TM2 (SFDi = 1) and TM1

2-265

Page 35

Image 35

Mitel MT90840 manual Serial Port with Negative Polarity F0 ST-BUS, Serial Port with Positive Polarity F0 GCI

Contents

Applications FeaturesPin Connections PIN PlccNo Connection Pin DescriptionPin # Description 100TDI PckrPckt Ground +5 Volt Power SupplyDevice Operation Time Slot Interchange Operation SwitchingFunctional Description Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps PPFRi PDi0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Asynchronous Parallel Port With ST-BUS Clock Master Timing and Switching ControlOutput Driver Enable Control Capability Timing Mode 1 TM1 Ring MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = Per-channel Control Outputs on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Bypass on the Parallel PortMT90840 Throughput Delay Summary Mode Data Rates Minimum Delay Total Throughput DelayPer-channel Direction Control on the Serial Port Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Tri-state Serial and ParallelAddressing Serial Data Memory Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing DTA Data Transfer Acknowledgment Pin Microprocessor PortAddress Mapping of the Internal Registers IRQ Interrupt PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Memory Block-Programming Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Detecting Clock PresenceJtag Support Timing Mode InitializationBoundary-Scan Instruction Register Test Access Port TAPBoundary-Scan Instruction Register I01 Instruction DescriptionHigh Test Data RegistersCells Deﬁnition Boundary-Scan Register Cells DeﬁnitionsDR1 Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE Register DescriptionAlarm Status Register ALS READ/WRITE General Purpose Mode Register GPM READ/WRITEControl Register CR READ/WRITE Phase Status Registers PSD Read OnlyAB9 AB8 Internal Memory DescriptionAB11 AB10 CTI Distributed Architecture Implemented with the MT90840 Distributed Isochronous NetworkAbsolute Maximum Ratings Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Characteristics Sym Min Typ‡ Max Units Test Conditions/PinsTM1 Characteristics Sym Min Typ‡ Max Units Test ConditionsOutput Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Positive Polarity F0 GCI Serial Port with Negative Polarity F0 ST-BUSSerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Positive Polarity Spfp = F0 Frame Sync with Negative Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Negative Polarity Spfp = Frame Sync with Positive Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 Parallel Port Receive Timing AC Electrical Characteristics Parallel Data PortParallel Port in Timing Mode 774 Up to 3 C4 cycles + Register takd-wr RD/WRAD0 Intel/National Multiplexed Bus TimingCharacteristics Sym Min AC Electrical Characteristics† Motorola Multiplexed Bus ModeAD0-13 AD0-7Boundary Scan Test Port Timing Parameter Symbol Min Max Units Test ConditionsNot to scale Dimensions in inches are not exactDim Min Max 280