Mitel MT90840 manual Control Register CR READ/WRITE, Phase Status Registers PSD Read Only

MT90840	Preliminary Information
Control Register (CR) - READ/WRITE

SEL2 SEL1

SEL0 HA11

HA10

HA9

HA8

HA7

7 6 5 4 3 2 1 0

This register selects which 128 byte page of which internal memory will be accessed by the CPU when the address bit AD<7> is high. (When address bit AD<7> is low, the control registers are accessed.)

SEL2-0Memory Select bits. Used by the CPU to select the internal memories of the MT90840 for read or write operations. SEL2-0 bits have to be written before any READ/WRITE operation is performed on the internal memories.

SEL2	SEL1	SEL0	Memory Selected for RD/WR operation
0	0	0	Receive Path Connection Memory Low (RPCM Low)
0	0	1	Receive Path Connection Memory High (RPCM High)
0	1	0	Receive Path Data Memory (RPDM)
0	1	1	Enable Memory Block-Programming feature for RPCM High
1	0	0	Transmit Path Connection Memory Low (TPCM Low)
1	0	1	Transmit Path Connection Memory High (TPCM High)
1	1	0	Transmit Path Data Memory (TPDM)
1	1	1	Enable Memory Block-Programming feature for TPCM High

HA11-7High Address Bits 11-7. These bits select which 128 byte page of the selected memory (see SEL2-0 bits) will be accessed by the CPU. Used along with AD0-AD6 input lines to address the MT90840 internal memories when the address bit AD<7> is high. See RPCM, TPCM, RPDM and TPDM Address Mapping section for more details.

To address serial time slots in TPDM or RPCM:

	Serial Port	Number of Serial Port	HA bits and input address lines, or	HA bits and input address lines, or
	Data Rate	Input and Output	TPCM address bits, used to select	TPCM address bits, used to select the
		Streams	ST stream.	time slot.
2	Mbps Balanced	8i x 8o (256 channels)	HA7 + AD6-AD5 / AB7-AB5	AD4-AD0 / AB4-AB0 (32 time slots)
2	Mbps Add/Drop	16 i/o (512 channels)	HA8-HA7 + AD6-AD5 / AB8-AB5	AD4-AD0 / AB4-AB0 (32 time slots)
4	Mbps	8i x 8o (512 channels)	HA8-HA7 + AD6 / AB8-AB6	AD5-AD0 / AB5-AB0 (64 time slots)
8	Mbps	4i x 4o (512 channels)	HA8-HA7 / AB8-AB7	AD6-AD0 / AB6-AB0 (128 time slots)

To address parallel time slots in RPDM or TPCM:

Parallel Port	Number of Channels	HA bits and input address lines used	RPCM address bits used to select chan-
Data Rate		to select channel in TPCM.	nel.
19.44 Mbyte/s	2430	HA11-HA7 + AD6-AD0	AB11-AB0
16.384 Mbyte/s	2048	HA10-HA7 + AD6-AD0	AB10-AB0
6.480 Mbyte/s	810	HA9-HA7 + AD6-AD0	AB9-AB0

Phase Status Registers (PSD) - READ Only

PSD7 PSD6 PSD5 PSD4 PSD3

PSD2 PSD1

PSD0

Register Address 8 (Low Byte)

7 6 5 4 3 2 1 0

0	0	0	0	0	PSD10	PSD9	PSD8
7	6	5	4	3	2	1	0

Register Address 9 (High 3-bits)

PSD10-0Phase Status Data 10-0. The PSD bits represent the phase status of the serial port, as sampled at every second PPFRi frame (every 250 μsec). PSD0 is the phase of the internal 4.096 MHz clock, PSD1-9 count the cycles of the 4.096 MHz within a frame, and PSD10 toggles each frame (even/odd frame bit). The PSD bits enable the CPU to monitor the relative phases of the Receive parallel port and the serial port. This is especially useful in TM1, where the PSD bits might be used by the CPU to monitor a PLL control loop, since the elastic buffer in the Receive parallel port allows great variation in phase. These registers should be read twice in succession, in case the CPU access occurs close to the sampling edge.

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