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Mitel MT90840 manual Rd/Wr, Up to 3 C4 cycles + Register takd-wr

Models: MT90840

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MT90840

Preliminary Information

AC Electrical Characteristics† - Intel/National- HPC Multiplexed Bus Mode

Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions/

Notes

1

ALE pulse width

talw

10

ns

2

Address setup from ALE falling

tads

5

ns

3

Address hold from ALE falling

tadh

5

ns

4

Active after ALE falling

talrd

15

ns

RD

5

Data setup from

LOW on read

tddr

0

ns

CL=150 pF on

DTA

DTA,

and 30 pF on AD0-7.

6

hold after

tcsrw

0

ns

CS

RD/WR

7

setup from

tcsr

0

ns

CS

RD

8

Data hold after

tdhr

10

22

ns

CL=30 pF

RD

15

30

ns

CL=150 pF

9

delay after ALE falling

talwr

15

ns

WR

10

setup from

tcsw

0

ns

CS

WR

11

Data setup from

tdsw

10

ns

WR

12

Data hold after

Inactive

tdhw

0

ns

WR

13

trst

23

ns

RD/WR Inactive to ALE Falling Edge

14

Acknowledgment hold time

takh

0

20

ns

CL=150 pF, RL=1kΩ∗

15

Data Delay on Reading Registers

trdd

47

ns

CL=30 pF

68

ns

CL=150 pF

16

Acknowledgment Delay

takd-rd

73

ns

CL=30 pF

Reading Registers

85

ns

CL=150 pF

Acknowledgment Delay

takd-wr

32

ns

CL=30 pF

Writing Registers

41

ns

CL=150 pF

17

Acknowledgment Delay - Memories:

takd-mem

Reading TP Data Memory

244

488

1306

ns

1 to 5 C4 cycles +

register takd-rd

Reading RP Data Memory

122

366

1062

ns

.5 to 4 C4 cycles +

register takd-rd

Reading TP Connection Memory

1 clock

2 clock

3 clk cyc +

1 to 3 PCKT/R cycles

cycle

cycles

takd-rd

+ register takd-rd

Reading RP Connection Memory

244

488

817

ns

1 to 3 C4 cycles +

register takd-rd

Writing TP Connection Memory**

takd-wr

3 clk cyc +

Up to 3 PCKT/R cyc.

takd-wr

+ register takd-wr

Writing RP Connection Memory**

takd-wr

774

ns

Up to 3 C4 cycles +

register takd-wr

† Timing is over recommended temperature & power supply voltages.

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

*High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

**Individual writes to Connection Memories will have Register Acknowledgment Delay. Burst writes to Connection Memories will have Read Connection Memory Acknowledgment Delay.

2-274

Image 44

Mitel MT90840 manual Rd/Wr, Up to 3 C4 cycles + Register takd-wr

Contents

Features ApplicationsPIN Plcc Pin ConnectionsPin Description Pin #Description 100 No ConnectionTDI PckrPckt +5 Volt Power Supply GroundDevice Operation Time Slot Interchange Operation SwitchingFunctional Description C4/8R1&2 4 MHz Serial I/O 2 Mbps Serial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 MbpsPPFRi PDi0-7 Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Receive Path Bypass/Parallel-Switching PathTransmit Path Serial Data Port Parallel Data Port Parallel Port Clock Signals and FramingSerial Frame Pulse Timing and Switching Control Output Driver Enable Control CapabilityTiming Mode 1 TM1 Ring Master Asynchronous Parallel Port With ST-BUS Clock MasterAsynchronous Parallel Port With ST-BUS Clock Slave Timing Mode 2 TM2 Ring SlaveTM1 Multiple-MT90840 Sub-Mode Pfdi TM2 Multiple-MT90840 Sub-Mode Sfdi External PLL and C4 Phase-CorrectionInternal 4.096 MHz Clock Divider Sfdi = MT90840 Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Throughput Delay MT90840 Per-channel FunctionsPer-channel Bypass on the Parallel Port Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Message Mode Serial and Parallel STi0 STo0Per-channel Tri-state Serial and Parallel Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing Microprocessor Port Address Mapping of the Internal RegistersIRQ Interrupt Pin DTA Data Transfer Acknowledgment PinMT90840 Register Address Mapping Accessing Internal MemoriesHex Clock Quality and TM1 Tpcm Access Integrity Clock Quality and TM2 Rpcm Access IntegrityDetecting Clock Presence Memory Block-ProgrammingTiming Mode Initialization Jtag SupportTest Access Port TAP Boundary-Scan Instruction RegisterI01 Instruction Description Boundary-Scan Instruction RegisterTest Data Registers Cells DeﬁnitionBoundary-Scan Register Cells Deﬁnitions HighInterface Mode Selection Register IMS READ/WRITE Timing Mode Register TIM READ/WRITERegister Description DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Parameter Symbol Min Max Units Characteristics Sym Min Typ Max Units Test ConditionsCharacteristics Sym Min Typ‡ Max Units Test Conditions/Pins Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Output Pin Test Point Characteristics Sym Min Typ‡Units Test Conditions Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingNot to scale Dimensions in inches are not exactDim Min Max 280