Mitel MT90840 AC Electrical Characteristics Parallel Data Port, Parallel Port Receive Timing

MT90840 Preliminary Information

PCKR

PDi0-7

PPFRi

	tclkh	tclkl
		tclk
tstis	tstih
Byte 0		Byte 1
tfs	tfh

Figure 28 - Parallel Port Receive Timing

AC Electrical Characteristics - Parallel Data Port

	Characteristics	Sym	Min Typ‡	Max	Units	Test Conditions
1	PCKT/PCKR clock period	tclk	50		ns
2	PCKT/PCKR HIGH time	tclkh	20		ns
3	PCKT/PCKR LOW time	tclkl	20		ns
4	PPFTo output delay	tdf		28	ns	CL=30pF
	from PCKR/PCKT transmit edge			30		CL=50pF
5	PDo output delay	tsod		28	ns	CL=30pF
	from PCKR/PCKT transmit edge			30		CL=50pF
6	CTo0-3 output delay	tcdf		26	ns	CL=30pF
	from PCKR/PCKT transmit edge			28		CL=50pF
7	PDo delay from Active to High-Z	tza		26	ns	CL=30pF, RL=1K
8	PDo delay from High-Z to Active	taz		28	ns	CL=30pF, RL=1K
9	PPFRi Setup Time	tfrs	5		ns
	from PCKR sampling edge
10	PPFRi Hold Time	tfrh	8		ns
	from PCKR sampling edge
11	PDi Set-up Time	tstis	5		ns
	from PCKR sampling edge
12	PDi Hold Time	tstih	8		ns
	from PCKR sampling edge
13	PPFTi Input Setup Time	tppfs	5		ns	TM1, PFDI = 1
	from PCKT sampling edge
14	PPFTi Input Hold Time	tppfh	5		ns	TM1, PFDI = 1
	from PCKT sampling edge
15	Jitter between PCKT/PCKR and	tpv	-100	+100	ns	C4/8R1 or C4/8R2 at 4.096
	C4 serial port clock.					MHz with 50% duty cycle

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

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