Mitel MT90840 manual Mode Data Rates Minimum Delay Total Throughput Delay

MT90840				Preliminary Information
	Mode	Data Rates	Minimum Delay	Total Throughput Delay
	TM1, TM2,	All	Dmin = 7.7 μsec	D = Dmin + 1 frame + Po - Si = 132.7 μsec + Po - Si
	or TM3 S/P		Note 1	Min. 7.7 μsec, Avg. 133 μsec, Max. 258 μsec
	TM1P/S	All	Dmin = ELDmin	D = 1 frame + ELD + So - Pi = 125 μsec + ELD + So - Pi
			= 4.4 μsec	Min. 4.4 μsec, Max. 379 μsec
			Note 2
	TM2 P/S	All	Dmin = 4.3 μsec	D = Dmin + 1 frame + So - Pi = 129.3 μsec + So - Pi
			Note 1	Min. 4.3 μsec, Avg. 129 μsec, Max. 254 μsec
	TM3 P/S	All	Dmin = 1 frame -	T = Dmin + 1 frame + So - Pi = 242.3 μsec + So - Pi
			7.7 μsec	Min. 117 μsec, Avg. 242 μsec, Max. 367 μsec
			= 117.3 μsec
	TM1 P/P	All	Dmin = 12 μsec +	D = 7.7 μsec + 1 frame + ELD
	(Bypass)		1 frame	Min.137 μsec, Max. 262 μsec
			= 137 μsec
			Note 2
	TM2 P/P	19.44 Mbyte/s		D = {235 or 235.5} PCKR cycles = 12 μsec
	(Bypass)	16.384 Mbyte/s	Note 3	D = {199 or 199.5} PCKR cycles = 12 μsec
		6.480 Mbyte/s		D = {80 or 80.5} PCKR cycles = 12 μsec
	TM4 P/P	19.44 & 16.384	Dmin = {3.5 or 4}	D = Dmin + 1 frame + Po - Pi
	(Switching)	Mbyte/s	PCKR cycles	Min. < 0.3 μsec, Avg. 125 μsec, Max. 250 μsec
			(TCP bit = 1 or 0)
	TM1 S/P +	All	Dmin = 12 μsec +	D = 12 μs + 2 frames + Transmission + So - Si
	TM2 P/S		1 frame	= 262 μsec + Transmission + So - Si
			= 137 μsec
	TM2 S/P +	All	Dmin = 12 μsec +	D = 12 μsec + 2 frames + Transmission + ELD + So - Si
	TM1 P/S		1 frame	= 262 μsec + Transmission + ELD + So - Si
			= 137.4 μsec
	TM1 S/P +	All	Dmin = 4 frames	D = (2 X 12) μsec + 4 frames + 2 X Transmission + ELD
	TM2 P/S +		= 500 μsec	+ So - Si = {5 or more integral frames} + So - Si
	TM2 S/P +			(Note 4)
	TM1 P/S
	TM1 S/P +	All	Dmin = 2 frames	D = (3 X 12) μsec + 2 frames + 2 X Transmission + ELD
	TM2		= 250 μsec	+ So - Si
	Bypass +			= {3 or more integral frames} + So - Si
	TM1 P/S			(Note 4)
	TM3 S/P +	All	Dmin = 250 μsec	D = (7.7 + 117.3) μsec + 2 frames + So - Si
	TM3 P/S			= 375 μsec + So - Si
				Min. 250 μsec, Avg. 375 μsec, Max. 500 μsec (Note 4)
		Table 1 - MT90840 Throughput Delay Summary

Naming rules:

ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4 μsec).

P/S:Parallel-to-Serial data path.

Pi:Parallel Input channel time, expressed in delay after PPFRi (0 to 125 μsec).

Po:Parallel Output channel time, expressed in delay after PPFTi/o (0 to 125 μsec).

S/P:Serial-to-Parallel data path.

Si:Serial Input channel time, expressed in delay after F0i/o (0 to 125 μsec). So: Serial Output channel time, expressed in delay after F0i/o (0 to 125 μsec).

Transmission:The delay due to electronic circuits and physical media connecting the parallel ports of two MT90840s. (Assumed to be negligible in TM3.)

Note 1: Exact P/S or S/P delay depends on relative positions of PPFRi and F0 +/- 120 nsec tolerance).

Note 2: Actual TM1 P/S and P/P delay depends on elastic position of PPFRi with respect to F0i (see ELD definition).

Note 3: Bypass delay in TM2: PPFT and PDo ch.0 are co-incident with PDi ch.235 at 19.44 MHz, ch.199 at 16 MHz, and ch.80 at 6.48 MHz. (TCP = 1 delays PDo ch.0 an extra half clock-cycle in TM2).

Note 4: “Round-trip” delay from/to serial ports with the same F0 is always an integral number of frames (plus switching: So - Si).

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