Mitel MT90840 manual Characteristics Sym Min Typ‡, Units Test Conditions, Output Pin Test Point

MT90840				Preliminary Information
AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics	Sym	Min Typ‡	Max	Units	Test Conditions
10 STo Delay from High-Z to Active	tza				CL=30pF, RL=1K
2.048 and 4.096 Mbps (TM2 &TM3)			38	ns
2.048 and 4.096 Mbps (TM1)			50	ns
8.192 Mbps (STio0-3)			26	ns
11 STo Output Delay from SPCKo	tsod		40	ns	CL=30pF
(TM2 & TM3, 2.048 and 4.096 Mbps)			64	ns	CL=150pF
STo Output Delay from 4.096 MHz C4/8			52	ns	CL=30pF
input (TM1)			72	ns	CL=150pF
STo 8.192 Mbps Output Delay from			28	ns	CL=30pF
C4/8 input (TM1, 2 & 3; STi/o0-3)			43	ns	CL=150pF
12 STi Input Setup Time from SPCKo	tstis	28		ns	SPCKo CL=30pF
output edge (2.048 and 4.096 Mbps)		41			SPCKo CL=150pF
STi Input Setup Time from C4/8 input
edge in TM1 (2.048 and 4.096 Mbps)		0		ns
STi Input Setup Time from C4/8 input					TM1 and TM2,
edge at 8.192 Mbps (STi/o0-3)		0		ns	STi0-3, STo0-3
13 STi Input Hold Time from SPCKo output	tstih	9		ns	SPCKo CL=30pF
edge (2.048 and 4.096 Mbps)		2			SPCKo CL=150pF
STi Input Hold Time from C4/8 input
edge in TM1 (2.048 and 4.096 Mbps)		20		ns
STi Input Hold Time from C4/8 input					TM1 and TM2,
edge at 8.192 Mbps		13		ns	STi0-3, STo0-3

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Output

Pin

Test Point

RL

S1

CL

VSS

VDD

S2

VSS

S1 is open circuit except when testing output levels or high impedance states.

S2 is switched to VDD or VSS when testing output

levels or high impedance states.

Figure 17 - Output Test Load

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