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Mitel MT90840 manual AC Electrical Characteristics† Motorola Multiplexed Bus Mode

Models: MT90840

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MT90840

Preliminary Information

AC Electrical Characteristics† - Motorola Multiplexed Bus Mode

Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions/

Notes

1

AS pulse width

tasw

10

ns

2

Address setup from AS falling

tads

5

ns

3

Address hold from AS falling

tadh

5

ns

4

Data setup from

LOW on

tddr

0

ns

CL=150 pF on

DTA

DTA,

read

30 pF on AD0-7.

5

hold after DS falling

tcsh

0

ns

CS

6

setup from DS rising

tcss

0

ns

CS

7

Data setup on write

tdsw

10

8

Data hold after write

tdhw

0

ns

9

DS Inactive to AS Falling Edge

tdss

23

ns

10

setup from DS rising

trws

5

ns

R/W

11

hold after DS falling

trwh

5

ns

R/W

12

Data hold after read

tdhr

10

22

ns

CL=30 pF

15

30

ns

CL=150 pF

13

DS delay after AS falling

tdsh

15

ns

14

Acknowledgment hold time

takh

0

20

ns

CL=150 pF,

RL=1kΩ∗

15

Acknowledgment Delay:

takd-wr

32

ns

CL=30 pF

Writing Registers

41

ns

CL=150 pF

Acknowledgment Delay:

takd-rd

73

ns

CL=30 pF

Reading Registers

85

ns

CL=150 pF

16

Memory Acknowledgment Delay

takd-mem

Reading TP Data Memory

244

488

1306

ns

1 to 5 C4 cycles +

register takd-rd

Reading RP Data Memory

122

366

1062

ns

.5 to 4 C4 cycles +

Reading TP Connection

1

register takd-rd

Memory

clock

2 clock

3 clk

1 to 3 PCKT/R

cycle

cycles

cyc +

cycles + register

takd-rd

takd-rd

Reading RP Connection

244

488

817

ns

1 to 3 C4 cycles +

Memory

register takd-rd

Writing TP Connection

takd-wr

3 clk

Up to 3 PCKT/R

Memory**

cyc +

cyc. + register takd-wr

takd-wr

Writing RP Connection

takd-wr

774

ns

Up to 3 C4 cycles +

Memory**

register takd-wr

† Timing is over recommended temperature & power supply voltages.

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

*High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

**Individual writes to Connection Memories will have Register Acknowledgment Delay. Burst writes to Connection Memories will have Read Connection Memory Acknowledgment Delay.

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Image 46

Mitel MT90840 manual AC Electrical Characteristics† Motorola Multiplexed Bus Mode, Characteristics Sym Min

Contents

Features ApplicationsPIN Plcc Pin ConnectionsDescription 100 Pin DescriptionPin # No ConnectionPckt PckrTDI +5 Volt Power Supply GroundFunctional Description Time Slot Interchange Operation SwitchingDevice Operation PPFRi PDi0-7 C4/8R1&2 4 MHz Serial I/O 2 MbpsSerial I/O 4 Mbps C4/8R1&2 8 MHz Serial I/O 8 Mbps Pckr or Pckt TCP bit = PPFTi/o Ppfp bit =1 PDo0-7Transmit Path Bypass/Parallel-Switching PathReceive Path Serial Data Port Serial Frame Pulse Parallel Port Clock Signals and FramingParallel Data Port Timing Mode 1 TM1 Ring Master Timing and Switching ControlOutput Driver Enable Control Capability Asynchronous Parallel Port With ST-BUS Clock MasterTM1 Multiple-MT90840 Sub-Mode Pfdi Timing Mode 2 TM2 Ring SlaveAsynchronous Parallel Port With ST-BUS Clock Slave Internal 4.096 MHz Clock Divider External PLL and C4 Phase-CorrectionTM2 Multiple-MT90840 Sub-Mode Sfdi Sfdi = Synchronous Parallel Port With ST-BUS Clock SlaveSfdi = MT90840 Per-channel Bypass on the Parallel Port MT90840 Throughput DelayMT90840 Per-channel Functions Per-channel Control Outputs on the Parallel PortMode Data Rates Minimum Delay Total Throughput Delay MT90840 Throughput Delay SummaryPer-channel Tri-state Serial and Parallel Per-channel Message Mode Serial and ParallelSTi0 STo0 Per-channel Direction Control on the Serial PortSerial Data Memory Addressing Addressing2.048 Mbps Add/Drop Mode Tpdm Addressing IRQ Interrupt Pin Microprocessor PortAddress Mapping of the Internal Registers DTA Data Transfer Acknowledgment PinHex Accessing Internal MemoriesMT90840 Register Address Mapping Detecting Clock Presence Clock Quality and TM1 Tpcm Access IntegrityClock Quality and TM2 Rpcm Access Integrity Memory Block-ProgrammingTiming Mode Initialization Jtag SupportI01 Instruction Description Test Access Port TAPBoundary-Scan Instruction Register Boundary-Scan Instruction RegisterBoundary-Scan Register Cells Deﬁnitions Test Data RegistersCells Deﬁnition HighRegister Description Interface Mode Selection Register IMS READ/WRITETiming Mode Register TIM READ/WRITE DR1General Purpose Mode Register GPM READ/WRITE Alarm Status Register ALS READ/WRITEPhase Status Registers PSD Read Only Control Register CR READ/WRITEInternal Memory Description AB9 AB8AB11 AB10 Distributed Isochronous Network CTI Distributed Architecture Implemented with the MT90840Characteristics Sym Min Typ‡ Max Units Test Conditions/Pins Parameter Symbol Min Max UnitsCharacteristics Sym Min Typ Max Units Test Conditions Absolute Maximum RatingsCharacteristics Sym Min Typ‡ Max Units Test Conditions TM1Units Test Conditions Characteristics Sym Min Typ‡Output Pin Test Point Serial Port with Negative Polarity F0 ST-BUS Serial Port with Positive Polarity F0 GCISerial Port Timing for 2.048 Mbps TM2 SFDi = 0 and TM3 267 F0 Frame Sync with Negative Polarity Spfp = F0 Frame Sync with Positive Polarity Spfp =Serial Port Timing for 8.192 Mbps TM1 and TM2 SFDi = Frame Sync with Positive Polarity Spfp = Frame Sync with Negative Polarity Spfp =Timing for the Parallel Port External Control Lines CTo0-3 AC Electrical Characteristics Parallel Data Port Parallel Port Receive TimingParallel Port in Timing Mode RD/WR 774 Up to 3 C4 cycles + Register takd-wrIntel/National Multiplexed Bus Timing AD0AC Electrical Characteristics† Motorola Multiplexed Bus Mode Characteristics Sym MinAD0-7 AD0-13Parameter Symbol Min Max Units Test Conditions Boundary Scan Test Port TimingDim Min Max Dimensions in inches are not exactNot to scale 280