Mitel MT90840 Serial Frame Pulse, Parallel Data Port, Parallel Port Clock Signals and Framing

MT90840 Preliminary Information

Register enables the internal divider, and the SPCKo output (and internal 4.096 MHz clocks) are driven by the clock divided-down from PCKR. At 16.384 MHz, this is a simple divide-by-4, and the SPCKo output jitter will depend on the PCKR input jitter. At 19.44 MHz, the SPCKo output jitter will be larger as the divider switches between rising and falling edges of PCKR. The serial port timing and F0o frame pulse are tightly slaved to PPFRi when INTCLK is set high.

Serial Frame Pulse

In TM1, the MT90840 receives the frame reference (F0i) from an external source, and the MT90840 senses the polarity of the frame pulse and adapts the device timing to the appropriate (ST-BUS or GCI) format.

In TM2 and TM3, the MT90840 outputs the serial port frame pulse (F0o). Positive (GCI) or negative (ST-BUS) frame pulse formats, and the associated clock polarity, can be selected for the F0o signal by programming the SPFP bit in the GPM Register. This flexibility allows the MT90840 to be employed with different serial bus formats.

In applications which require a large number of serial channels in TM2, it is possible to operate multiple MT90840s in parallel using the SFDI control bit (in the TIM register). To allow the MT90840s to synchronize their internal timing, all of the MT90840s are connected to the same C4/8 reference source, and one MT90840 in normal TM2 (SFDI set low) supplies F0 to one or more MT90840s in TM2 with SFDI set high. With SFDI set high, F0 becomes an input, and this allows the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal 4.096 MHz clock divider is used (INTCLK high) it is not necessary to use the SFDI control, as the serial port timing and F0o frame pulse of each parallel MT90840 will be tightly slaved to PPFRi when INTCLK is set high.

Should the input framing at F0i cease while the C4/8 clock continues to run, the MT90840 will continue to function as if the frame pulse was asserted after the normal number of clock cycles (free run). If F0i re-commences the MT90840 will immediately sync to F0i, but changes in the F0i interval will temporarily disrupt the TDM data streams. If the F0i input is held asserted, the serial I/O will “lock up” and operation will be disrupted.

Parallel Data Port

The MT90840 parallel port is composed of an 8-bit wide Parallel Data Output Port (PDo0-7), a 4-bit wide Control output port (CTo0-3), an 8-bit wide Parallel

Data Input Port (PDi0-7), a Receive Frame sync signal (PPFRi) and a Transmit Frame sync signal (PPFT), and Transmit (PCKT) and Receive (PCKR) Clocks.

The Parallel Port Rates are controlled by the PPS bits in the IMS register, and are:

•19.44 Mbyte/s (2430 channels),

•16.384 Mbyte/s (2048 channels), and

•6.48 Mbyte/s (810 channels).

The user can further specify the features of the parallel TDM port, including:

•the edge of the parallel port clock used to transmit data and PPFTo (see TCP bit in the TIM register),

•the polarity of the Parallel Port Frame Transmit pulse PPFT (see PPFP bit in the GPM register),

•the use of PPFT (normally an output) as an input in TM1, if the application requires multiple MT90840 devices to operate in parallel (see PFDI bit in the TIM register).

The parallel port of the MT90840 is flexible enough to interface to a variety of applications. It can be connected to a framer to access a serial transport backbone running at up to 155 Mbps. It can be connected to a backplane-type parallel bus. It can share a parallel bus with other devices, using the control outputs (CTo0-3) and the per-channel tristate function to share access to the bus.

Parallel Port Clock Signals and Framing

The MT90840's PPFRi (Parallel Port Frame pulse Receive input) and PPFTi/o (Parallel Port Frame pulse Transmit i/o) signals synchronize the MT90840 to the high speed data frame. Receive data is clocked in at the Parallel Data inputs (PDi0-7) by the Parallel port Receive ClocK (PCKR), as framed by Receive Parallel Port Frame input (PPFRi). In TM2, TM3 and TM4, PCKR also clocks the Parallel Data outputs (PDo0-7), with the framing in TM2 and TM4 indicated by the PPFTo output. In TM1, the Parallel Data outputs are clocked out by PCKT, with the framing indicated by PPFTo. Alternatively, the Transmit framing can be controlled by the PPFTi input if the PFDI bit in the TIM register has been set high, to enable multiple MT90840s to operate in parallel in TM1.

Should the input framing at PPFRi cease while the PCKR clock continues to run, the MT90840 will continue to function as if the frame pulse was asserted after the normal number of clock cycles (free run). If PPFRi re-commences, the MT90840 will immediately sync to PPFRi, but any change in the framing interval will temporarily disrupt the TDM data

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