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MT90840 | Preliminary Information |
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| Serial Input | TPDM |
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| STi0, Ch0 |
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| CPU Port Addressing: |
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| STi0, Ch1 |
| 001H |
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| CAR |
| Address Bus |
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| 1 | 0 |
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| 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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| STi3, Ch126 | 1FEH |
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| STi4, Ch127 | 1FFH |
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| TPCM Contents: |
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| 8 | 7 |
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| 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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| Bits 8:7 select one of 8 streams. |
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| Bits 6:0 select one of 128 |
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| channels per stream. |
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| Figure 14a - 8.192 Mbps TPDM Addressing | ||||||||||||||||||||
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| Serial Output | RPCM |
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| STo0, Ch0 |
| 000H |
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| CPU Port Addressing: |
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| STo0, Ch1 |
| 001H |
| CAR |
| Address Bus |
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| 1 | 0 |
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| 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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| Stream |
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| STo3, Ch126 | 1FEH |
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| STo4, Ch127 | 1FFH |
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Figure 14b - 8.196 Mbps RPCM Addressing
Microprocessor Port
An
The MT90840 CPU interface signals are
Accesses from the microport to the Connection and Data Memories are multiplexed with accesses from the input and output TDM ports. This can cause variable data acknowledge delays which are communicated to the CPU by the DTA output signal.
Note that if the parallel port clocks PCKR & PCKT or serial port clocks C4/8R1 & C4/8R2 are not present during an internal memory access, the DTA output signal may be held HIGH until the clocks are applied again.
For complete details on the Microprocessor Interface timing signals, refer to the AC Electrical Characteristics section.
Address Mapping of the Internal Registers
The MT90840 provides internal registers which are used by the CPU to configure the device in the various operation modes. The IMS, TIM, GPM and ALS Registers should be initialized by the CPU on every system
When input address pin AD7 is HIGH, input address pins
IRQ Interrupt Pin
The MT90840 provides the output pin IRQ (Interrupt Request) which is active HIGH and indicates the occurrence of one or more error conditions in the MT90840 timing operations. The occurrences are indicated by bits PPCE, RXPAA, TXPAA and FSA in the ALS Register.
Except for cases where the indications are masked by the
To cause the IRQ output signal or the indication bits to return to LOW again, the CPU can write any value to the ALS Register (normally the Mask bits are
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then switches to