Mitel MT90840 manual Jtag Support, Timing Mode Initialization

Preliminary Information MT90840

DR1-0 and FDC in the IMS register) before programming the RPCM.

b)The GPM Register is written. The CPU sets the Block-Programming Enable (BPE) bit to HIGH and the Block-Programming Data (BPD7-4) bits to the desired value. This action causes the contents of the BPD7-4 bits to be loaded into the four most significant bits of all addresses in TPCM High, or RPCM High (as set by the Control Register).

c)The user waits 250 μsec (two frames) to allow the TPCM High (2430 positions) or RPCM High (512 positions) to be entirely loaded with the new pattern.

d)After 250 μsec, the user should check that the BPE bit is LOW, indicating that the Block Program completed successfully. If the BPE bit does not return to LOW, the necessary TDM clock input may not be available. The BPE bit can be written LOW to force an end to the Block Programming.

Procedures a, b, c, and d must be performed twice if both TPCM and RPCM have to be initialized.

Block-programming requires stable F0 and PPFRi framing to function properly. If the framing jumps during block-programming, a section of memory may be missed. RPCM block-programming is dependent on the C4/8 serial port clock and F0 framing. TPCM block programming is dependent on the PCKT clock, and F0 framing (PCKR, PPFRi and F0 in TM2). DIN should not be active during block programming.

If there is some doubt about the quality of the clocks in a particular application, block-programming options include:

-1- If a stable C4/8 serial port clock is not available, or if a stable F0i frame is not available, use TM2 with

Internal Clocks (INTCLK=1) to perform block-programming of RPCM.

-2- If stable PPFRi framing is not available in TM2, disable the external gate driving PPFRi and use free-running framing to perform block-programming of TPCM (and/or Internal Clocks mode to block-program RPCM).

The interrupt source bits can also be monitored during block-programming. If PPCE, or RXPAA (in TM2), or TXPAA (in TM1), is asserted during block-programming, a framing error has occurred and the block-programming should be repeated.

Timing Mode Initialization

On system power-up, the CPU should program the MT90840 IMS, GPM, and TIM registers to establish the data rates, the Timing Mode (1,2,3,4), and the framing polarity of the device. The MT90840 will then adjust its internal rate conversion and time interchange circuits to accommodate the different rates set at both data ports.

To perform the rate conversions between the serial and the parallel ports, the MT90840 provides a phase alignment circuit, monitored by the RXPAA and TXPAA interrupt bits. In TM1 and in TM2 with external clocks (INTCLK=0) the phase alignment circuit works automatically to maintain the relative phase of the serial and parallel ports. The DIN bit in the GPM register works with this circuit by reducing the window, forcing the phase alignment circuit to center the relative phases.

After the parallel and serial port reference clocks (PCKT/PCKR and C4/8R1/C4/8R2) are stable, the DIN bit in the GPM Register can be set HIGH. The DIN bit will auto-reset itself after 8 frames, returning to LOW. (It can also be written LOW by the CPU.) The DIN bit procedure is especially useful in TM2. In TM1 the DIN bit also centers the phase relation, but the movement of the transmit parallel port timing during the 8 frames that DIN is asserted may cause data or framing errors in connected devices. The RPCM and TPCM should not be written to by the CPU while DIN is asserted.

JTAG Support

BOUNDARY -SCAN CELL(BSC)

BSC	BSC	BSC	BSC	T	TEST DATA IN (TDI)
				A
				P
				C	TEST CLOCK (TCK)
				O
	CORE LOGIC			N
				T	TEST MODE
				R
				O	SELECT (TMS)
				L
				L
BSC	BSC	BSC	BSC	E	TEST DATA OUT (TDO)
				R

Figure 15 - A Typical Boundary-Scan IC

The MT90840 boundary-scan circuitry functions in accordance with IEEE Std 1149.1a (often referred to as JTAG boundary-scan). The standard specifies a

design-for-testability technique called Boundary-Scan Test (BST). A boundary-scan IC has

ashift-register stage or ‘Boundary-Scan Cell’ (BSC) in between the core logic and the I/O buffers adjacent to each I/O pin. The boundary-scan cellscan control and observe what happens at each

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