NEC PD75402A manuals
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195 pages 877.34 Kb
USER'S MANUAL PD75402A4 PREFACE USEROBJECTIVE COMPOSITION READING LEGEND 9 CONTENTS OF FIGURES Fig. No Title Page10 Fig. No. Title Page11 Table No. Title Page12 CHAPTER 1. GENERAL13 21.1 OUTLINE OF FUNCTIONS 16 51.4 BLOCK DIAGRAM PD75P402. Remarks Parentheses for the 18 7(2) PROM mode 19 81.5.2 44-Pin Plastic QFP ( 10mm) (1) Normal operating mode PD75P402s VPP is to be set to the GND potential. PD75P402 and the printed circuit board commonly in the Remarks Parentheses for the PD75P402. *If using the PD75402A, the NC pin of the 30-pin corresponding to the 20 9(2) PROM mode 21 CHAPTER 2. PIN FUNCTIONS22 112.1 Remarks 1. In the PD75402A PIN FUNCTION LIST 2.1.1 Port Pin List Table 2-1 Port Pin List 23 122.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins PD75P402 and the printed circuit board commonly, the NC pin should be connected directly to VSS. Remarks For the status of each pin at reset, see CHAPTER 8 RESET FUNCTION. *If using the 29 VV P.U.R. P-ch P.U.R. enable IN P-ch N-ch OUT data output disableP-ch IN/OUT data output disable P.U.R. P.U.R. enable P-ch IN/OUT P.U.R. data output disable P.U.R. enable 30 IN/OUTdata output disable 32 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP33 22Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode 34 23Table 3-2 Addressing Mode List 40 29Table 3-4 PD75402A I/O Map (1/2) Remarks 1. IE is an interrupt enable flag. 2. IRQ is an interrupt request flag. 41 30Table 3-4 PD75402A I/O Map (2/2) 42 CHAPTER 4. INTERNAL CPU FUNCTIONS43 ~ ~~~49 38CHAPTER 4. INTERNAL CPU FUNCTIONS Fig. 4-8 Data Saved to Stack Memory Fig. 4-9 Data Restored from Stack Memory 52 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS54 43Fig. 5-2 Configuration of Ports 0 and 1 56 45Fig. 5-4 Configuration of Ports 2 and 6 Internal Bus Output Latch 61 50Table 5-3 Operations with Input/Output Port Handling Instructions 67 56Fig. 5-11 Processor Clock Control Register Format s) as CPU clock. Note When using a calue of fXX such that 4.19 MHz < fXX 5.0 MHz, if maximum speed mode : fXX/4 (PCC1, PCC0 = 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 s and the standard minimum value 0.95 78 ()83 72Fig. 5-24 Serial Interface Block Diagram 95 120 109Fig. 5-46 ACKD Operation (a) When ACK signal is output in 9th SCK clock interval Fig. 5-47 BSYE Operation (c) Clearing timing when transfer start directive is given during busy state (b) When ACK signal is output after 9th SCK clock interval 110 Table 5-8 Signals in SBI Mode (1/2) 121 HSCK SB0 122 111Table 5-8 Signals in SBI Mode (2/2)1 2 7 8 1 2 7 8 9 10 SB0 SCK 123 125 114Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1) 126 115Fig. 5-50 Command Transmission from Master Device to Slave Device 127 116Fig. 5-51 Data Transmission from Master Device to Slave Device 128 117Fig. 5-52 Data Transmission from Slave Device to Master Device 132 134 135 136 165 ()154 Note Instruction Group 168 1572. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instruction 169 1582. Branch instructions 3. I/O instructions 4. CPU control instructions 170 MOV A, #n4MOV rp, #n8 MOV A, @HL 171 MOV @HL, AMOV A, mem MOV XA, mem MOV mem, A MOV mem, XA 172 XCH A, @HLXCH A, mem XCH XA, mem XCH A, reg1 173 MOVT XA, @PCXA174 ADDS A, #n4ADDS A, @HL ADDC A, @HL AND A, @HL 176 RORC ANOT A 182 BR addrBR $addr BRCB !caddr 183 CALLF !faddrRET RETS RETI 184 PUSH rpPOP rp 186 IN A, PORTnOUT PORTn, A188 177PD75402A and PD75402A. Since the 189 178190 179The following development tools are available for system development using the ~ PD75402A: Language Processor PROM Writing Tools 192 181Development Tool Configuration
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