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CONTENTS OF FIGURESFig. No Title Page3-1 Static RAM Address Updating Method ............................................................................................. 25
4-1 Program Counter Configuration......................................................................................................... 31
4-2 Program Memory Map ........................................................................................................................ 32
4-3 Data Memory Map ............................................................................................................................... 33
4-4 General Register Configuration.......................................................................................................... 35
4-5 Register Pair Configuration................................................................................................................. 35
4-6 Accumulators ........................................................................................................................................ 36
4-7 Stack Pointer Configuration................................................................................................................ 37
4-8 Data Saved to Stack Memory ............................................................................................................. 3 8
4-9 Data Restored from Stack Memory ................................................................................................... 38
4-10 Program Status Word Configuration................................................................................................. 39
5-1 Digital Input/Output Port Data Memory Addresses......................................................................... 41
5-2 Configuration of Ports 0 and 1 ........................................................................................................... 43
5-3 Configuration of Port 3 ....................................................................................................................... 44
5-4 Configuration of Ports 2 and 6 ........................................................................................................... 45
5-5 Configuration of Port 5 ........................................................................................................................ 46
5-6 Format of Port Mode Registers .......................................................................................................... 47
5-7 Format of Pull-Up Resistor Specification Register .......................................................................... 52
5-8 Pull-Up Resistor Incorporation Switching Timing ........................................................................... 5 2
5-9 Digital Input/Output Port Input/Output Timing ................................................................................ 53
5-10 Clock Generation Circuit Block Diagram........................................................................................... 54
5-11 Processor Clock Control Register Format......................................................................................... 56
5-12 System Clock Oscillation Circuit External Circuitry......................................................................... 57
5-13 Example of Poor Resonator Connection Circuit............................................................................... 57
5-14 Use of Variable Minimum Instruction Execution Time Function................................................... 59
5-15 Change of
Φ
after Power-On Reset.................................................................................................... 60
5-16 Clock Generation Circuit - Differences between
µ
PD75402A and
µ
PD75402 ............................... 61
5-17
µ
PD75402 Processor Clock Control Register Format....................................................................... 62
5-18 Clock Output Circuit Configuration.................................................................................................... 63
5-19 Clock Output Mode Register Format................................................................................................ . 64
5-20 Example of Remote Control Application........................................................................................... 65
5-21 Basic Interval Timer Configuration.................................................................................................... 66
5-22 Basic Interval Timer Mode Register Format..................................................................................... 67
5-23 Example of SBI System Configuration.............................................................................................. 71
5-24 Serial Interface Block Diagram........................................................................................................... 72
5-25 Serial Operating Mode Register (CSIM) Format.............................................................................. 75
5-26 Serial Bus Interface Control Register (SBIC) Format....................................................................... 78
5-27 Configuration Around Shift Register................................................................................................. 81
5-28 Example of 3-Wire Serial I/O System Configuration....................................................................... 84
5-29 3-Wire Serial I/O Mode Timing........................................................................................................... 88
5-30 RELT & CMDT Operation..................................................................................................................... 89
5-31 Shift Register (SIO) and Internal Bus Configuration....................................................................... 90