Iv Error occurrence, 125 | NEC PD75P402, PD75402A instruction

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(iv)Error occurrence

Operation in the event of an error in communication is described below.

A slave indicates the occurrence of an error by failing to return ACK to the master. When an error

occurs, the status bit indicating the occurrence of an error is set and all command processing being executed is canceled.

After sending or receiving a byte, the master checks for ACK from the slave. If ACK is not returned by the slave within a certain time after the end of transmission or reception, an error is judged to have occurred and the master outputs an ACK signal (as a dummy).

Fig. 5-61 Master and Slave Operations after an Error

Slave				End of Reception
				End of Reception
				Judges error to have occurred,
Processing				Judges error to have occurred,
Processing				stops processing
				stops processing


SB0	Error Data

						Wait Time
Master					ACK
					ACK


				Checks for ACK from slave
Processin				Checks for ACK from slave
Processin
				End of Transmission
				End of Transmission
				Start of ACK Check

ACK

Judges error to have occurred, outputs ACK

Errors are generated in the following circumstances:

•Errors generated on the slave side

➀If the command transfer format is wrong.

➁If an undefined command is received.

➂If the transferred data length is insufficient in a READ command.

4If the data storage area is too small in a WRITE command.

➄ If the data changes in a READ, STATUS or CHGMST command data transmission.

ACK is not returned if any of the above cases.

•Errors generated on the master side

If the data changes in a WRITE command data transmission, a STOP command is sent to the slave.

125

Image 136

NEC PD75P402, PD75402A Iv Error occurrence, Errors generated on the slave side, Errors generated on the master side, 125

Contents

ΜPD75402A Page Major Revisions in This Version Instruction Functions and Application Content to be read carefullyRemarks Related Documentation Device Related Documents Development Tool Related DocumentsOther Related Documents Latest documents should be used for design purposes, etc Contents Basic Interval Timer Interrupt Control Circuit ConfigurationDigital INPUT/OUTPUT Ports Clock Generation Circuit Standby Mode Setting and Operation States Standby Mode ResetOperation After Standby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Contents of Tables Table No Title FAX PPC GeneralECR VCR General Outline of Functions For details, see Interrupt Functions Ordering Information General Ordering Information and Quality GradeQuality Grade VPP Block Diagram PORT0 PORT1 PORT2 PORT3 PORT5INT0 Interrupt INT2 Control PORT6 General PIN Configuration SCKSO/SB0 VPP NC Prom mode 2 44-Pin Plastic QFP 10mm Normal operating mode NC NC NC P50P01/SCK NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions ΜPD75402A PIN Function List Port Pin List SCKSO/SB0 INT0 SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function Pins 5 INT2 ..... Port 1 Dual-Function Input 4 INT0 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output Reset Reset 7 X1, X2 Crystal PIN Functions Prom Mode CE Chip Enable ..... InputOE Output Enable ..... Input 1 A0 to A14 Address ..... Input PIN Functions PIN INPUT/OUTPUT Circuits Pin Input/output TypesRemarks a circle P22/PCL OUT IN/OUT Type F B Type M a P00, Reset PIN Functions Unused PIN Treatment Features of Architecture and Memory MAP Data Memory Bank Configuration Fbfh FB0HFF0H Fffh Addressing Mode List @HL Bit direct addressing mem.bit Data Memory Addressing ModesBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Stack addressing SUB Push POP RETPush HL POP Push HL Push XA RET Features of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware Operation ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Program Counter PC .... Bits Internal CPU FunctionsPC1 PC0 Program Memory ROM .... ,920 Words × 8 Bits Program Memory Map Internal CPU Functions Data Memory RAM Data areaGeneral register area Stack area Peripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 Bits Internal CPU Functions Accumulator Accumulators Internal CPU Functions Stack Pointer SP .... Bits Range of 020H to 03FHMOV SP, XA SP4 SP3 SP2 SP1 SP0 Data Saved to Stack Memory IST0 PSW Carry flag CY Internal CPU Functions Program Status Word PSW .... BitsCarry Flag Manipulation Instructions Interrupt Status Flag Indication Content SET1Skip flag SK2, SK1, SK0 Interrupt status flag IST0 Peripheral Hardware Functions PORT0 Digital Input/Output Port Types and Characteristics Csim Poga PO0PO1 INT2 INT0 Configuration of Port PO3 Configuration of Ports 2 Input/Output Mode Setting PM5 Pmgb Pmga Digital Input/Output Port Handling InstructionsFech PM5 PM2 Pmgb Bit handling instructions Operations when output mode is set Operations when input mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up Resistors PORT1 MOV POGA, XAFdch PO6 PO3 PO2 PO1 PO0 Digital Input/Output Port Input/Output Timing Data fetch by 2-machine-cycle instructionData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instruction Clock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Function and Operaion Processor clock control register PCCSEL MOV PCC, a FB3H PCC3 PCC2 PCC1 PCC0 PCC System clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry 13 Example of Poor Resonator Connection Circuit 2/2 Use of Variable Minimum Instruction Execution Time Function CPU Clock SettingExample 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU Clock Differences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1 Peripheral Hardware Functions Clock Output Circuit Clock Output Circuit ConfigurationP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Mode Register Clom Clom Clock Output Procedure Examle of Remote Control Application Peripheral Hardware Functions Basic Interval Timer Basic Interval Timer ConfigurationMPX BTM3 BTM2 Basic Intercal Timer Mode Register BTM MOV BTM. aBTM3 BTM Basic Interval Timer Operation From the beginning Examples of Basic Interval Timer Applications MOV BTM,AIebt SEL MOV Operation-halted mode Wire serial I/O modePeripheral Hardware Functions Serial Interface Serial Interface Functions SBI mode serial bus interface mode Serial Interface Configuration Serial Interface Block Diagram Functions Serial operating mode register Csim Serial bus interface control register SbicShift register SIO SO latch Intcsi control circuit Register Functions Serial operating mode register CsimSerial clock control circuit Serial clock selection bit W Serial interface operating mode selection bit WCsie COI WUP CSIM3 CSIM1 Csim Signal from address comparator R Csie MOV CSIM, XA SET1 CsieCsie CSIM3 Csie CSIM1 FE2H Cmdd Reld Cmdt Relt Command trigger bit W Command detection flag RBus release detection flag R Acknowledge trigger bit W Busy enable bit R/W Acknowledge detection flag R CLK SIOBUSY/ACK Error detection See 5.5.6 8 Error detection for detailsSlave address register SVA Slave address detection Register setting Csie C0I WUP CSIM3 CSIM1 Csim 5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System Configuration Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic 29 3-Wire Serial I/O Mode Timing Communication operation Serial Clock Selection and Use in 3-Wire Serial I/O Mode SignalsSerial clock selection Relt Cmdt Data transfer order Start of transfer Wire serial I/O mode applications MOV XA, TdataMOV SIO, XA SCK SO/SB0 MOV XA, Tdata SIO, XA IecsiMOV XA, Tdata XCH XA, SIO MOV RDATA, XA SBI Mode Operation + VDDCPU SB0 SCK SB0 SCK Address/command/data differentiation function Acknowledge signal ACK control functionBusy signal Busy control function SBI functions SBI definition SB0 ACKSB0 C0 ACK Busy SB0 D0 ACK Busy Bus release signal REL Command signal CMDSCK H SCK H SB0 Address 37 Slave Selection by Address Command & data Data Acknowledge signal ACK SCK SB0 ACK 100 Busy signal BUSY, ready signal ReadySCK SB0 ACK Busy 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105 RELT, CMDT, Reld & Cmdd Operation Slave 106SIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK 44 Ackt Operation 107 When Acke is set after completion of transfer When Acke = 0 on completion of transferWhen Acke = 1 interval is short 108 When ACK signal is output after 9th SCK clock interval 109SCK SB0 ACK Ackd SCK SB0 Bsye ACK 110 Signals in SBI Mode SCK CmddSB0 ACK Ready SB0 Ready 111 REL CMD Pin configuration Pin Configuration Diagram Use of slave address register SVA Address match detection method113 114 ChapterPeripheral Hardware 50 Command Transmission from Master Device to Slave 115 116 51 Data Transmission from Master Device to Slave Device 52 Data Transmission from Slave Device to Master Device 117 Points to note concerning SBI mode 118 Serial bus configuration SBI mode application119 Ii Communication procedure Description of commands Command types120 Iii Command formats ➀ Read command➁ WRITE, END and Stop commands 121 MSM 122ACK Stop ➂ Status command 123Status MSB LSB Reset command ➄ Chgmst command124 Chgmst Iv Error occurrence Errors generated on the slave sideErrors generated on the master side 125 Interrupt Functions 127 Interrupt Functions Interrupt Source Types and Vector Table Interrupt Request Source TypesVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0 Interrupt request flag & interrupt enable flag Interrupt Request Flag Setting SignalExample EI IE0 External interrupt input pin hardware 130 INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise Elimination Interrupt master enable flag IME 132FB4H IM03 FB2H IST0 Interrupt Servicing Status Interrupt status flag133 YES Interrupt Functions Interrupt SequenceIME=1 Interrupt INTxxx generation 136 Interrupt enabling/disabling Interrupt Functions Interrupt ApplicationsEI Iecsi Example using INTBT, INT0 falling edge active, and Intcsi 138CLR1 IRQ0 ➄ Reti 139 EI IE0➂ Intcsi Reti ➃ EI Iecsi Reti 140 Pending interrupt executionINT0 Intcsi ➁ Reti Halt mode Stop modeStandby Function Standby Function Standby Mode Setting and Operation States Standby Mode Operation States Standby Function Standby Mode Reset Stop mode reset by Reset inputHalt mode reset by Reset input Halt mode reset by interrupt generation 144 Halt Standby Function Operation After Standby Mode Reset IME = Reset Signal Acceptance Reset at Power-on 147 State of Hardware after ResetOFF Architecture and Memory MAP 148 Instruction SET Special Instructions Bit Manipulation InstructionsStack Instructions Example A0 Base Correction Instructions Base correction at additionAddc Adds Addc Operation identifier and description Instruction SET Instruction SET and ITS OperationOperation description legend Description of machine cycle field Description of addressing area field symbols152 Movt XA, @PCXA AddsAddc XOR 154 Instruction Group Instructions155 NOP Description of operation code symbols Instruction SET Operation Code of Each InstructionBit manipulation addressing operation code Iebt Iecsi IE0 IE2 Rorc Not Incs SET CLR SKT Not RET Rets Reti Push POP Halt Stop NOP Instruction SET Instruction Functions and Application Move InstructionsMOV A, #0BH MOV HL, #5FH MOV XA, 20H 160 MOV XCH Loop XCH161 Table Reference Instructions Table data on that162 02FFH See section Arithmetic and Logic Instructions163 Or A, @HL 164 Rorc a 165 Incs reg 166 SKE reg, #n4 167 Carry Flag Operation Instructions 168 Bit Manipuration Instructions 169 SKF mem. bit 170 BR addr 171 Subroutine Stack Control Instructions 172 Push rp 173 Interrupt Control Instructions 174 Input/Output Instructions 175 Halt 176 177 178 Prom Writing Tools Language Processor179 Debugging Tools 180 181 Development Tool ConfigurationIBM PC/AT 182 183 184 IrqcsPmgb Cmdd Port