CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
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(3) 8-bit direct addressing (mem)
An addressing mode to specify the whole data memory space directly by the instruction’s operand per 8 bits.
The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3EH and MB = 15
if it is 80H to FEH. Consequently, both the static RAM area of 000H to 03FH and the peripheral hardware area of FF0H
to FFFH are addressable. In the peripheral hardware area, however, the addresses capable of 8-bit manipulation
are limited. (See Table 3-4).
This addressing mode is applied to the MOV and XCH instructions.
Example 1. Store the serial interface shift register’s (SIO) 8-bit data at addresses 20H and 21H.
DATA EQU 020H
MOV XA, SIO ; XA ← SIO
MOV DATA, XA ; (21H) ← X, (20H) ← A
2. Take the 8-bit data input to the SIO into the XA register pair as well as setting the transfer data
stored in the XA register pair.
XCH XA, SIO ; XA ↔ SIO
(4) 4-bit register indirect addressing (@HL)
An addressing mode to specify the data memory space indirectly according to the content of the HL register per
4 bits.
The memory bank (MB) addressed in this addressing mode is fixed to to 0. Consequently, the static RAM area
of 000H to 03FH alone is addressable. The peripheral hardware area is not addressable. Data in the range of 00H
to 3FH should be set in the HL register pair.
This addressing mode is applied widely to data transfer, operation, compare, etc.
If combined with the HL register pair’s increase or decrease instruction (INCS, DECS), meanwhile, this addressing
mode allows the data memory space address to be updated freely.
Example Turn all the contents of 20H to 2FH into FH.
MOV HL, #2FH
MOV A, #0FH ; A ← FH
LOOP: MOV @HL, A ; (HL) ← A
DECS L
BR LOOP
Fig. 3-1 Static RAM Address Updating Method
× 0H × FH
0 × H
3 × F
DECS H
INCS L
DECS L
INCS H
@ HL 4-bit
Manipulation
Direct
Addressing
Bit
Manipulation
4-bit
Transfer
8-bit
Transfer