Internal CPU Functions Stack Pointer SP .... Bits | NEC PD75P402

CHAPTER 4. INTERNAL CPU FUNCTIONS

4.6STACK POINTER (SP) ..... 8 BITS

The μPD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address information of such a stack memory area is the stack pointer (SP). Fig. 4-7 shows its format.

As the SP’s high-order 3 bits are fixed to 001, the stack area is at the static RAM’s addresses 020H to 03FH. The SP is decremented before write (save) in the stack memory and is incremented after read (restore) from the

stack memory. Figs. 4-8 and 4-9 show the data saved and restored by each stacking operation.

The SP sets the initial value by the 8-bit data transfer instruction to determine the stack area. It is impossible to read the content of the SP.

Zero is always written in the SP’s bit 0.

It is recommended to initialize by writing 40H in the SP and use the built-in RAM’s maximum address (03FH) and beyond as the stack area.

The content of the SP turns indeterminate at RESET input, so it must be initialized to your desired value by the program initialization routine.

Note The SP of the Evachip packaged on the board for evaluation can address all the areas of 000H to 0FFH unlike in the μPD75402A. To eliminate such a difference at evaluation, the SP should be set not to access beyond

the range of 020H to 03FH.
Example SP initialize
MOV	XA, #40H
MOV	SP, XA	; SP ← 40H

Fig. 4-7 Stack Pointer Configuration

Address

F80H

7	6	5	4	3	2	1	0		Symbol

0	0	1	SP4	SP3	SP2	SP1	SP0		SP

							−
							0 Fixed

37

Image 48

NEC PD75P402 Internal CPU Functions Stack Pointer SP .... Bits, Range of 020H to 03FH, Mov Sp, Xa, SP4 SP3 SP2 SP1 SP0

Contents

ΜPD75402A Page Major Revisions in This Version Content to be read carefully Instruction Functions and ApplicationRemarks Related Documentation Device Related Documents Development Tool Related DocumentsOther Related Documents Latest documents should be used for design purposes, etc Contents Basic Interval Timer Interrupt Control Circuit ConfigurationDigital INPUT/OUTPUT Ports Clock Generation Circuit Standby Mode Setting and Operation States Standby Mode ResetOperation After Standby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Contents of Tables Table No Title General FAX PPCECR VCR General Outline of Functions For details, see Interrupt Functions General Ordering Information and Quality Grade Ordering InformationQuality Grade VPP Block Diagram PORT0 PORT1 PORT2 PORT3 PORT5INT0 Interrupt INT2 Control PORT6 General PIN Configuration SCKSO/SB0 VPP NC Prom mode 2 44-Pin Plastic QFP 10mm Normal operating mode NC NC NC P50P01/SCK NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions ΜPD75402A PIN Function List Port Pin List SCKSO/SB0 INT0 SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function Pins 4 INT0 ..... Port 1 Dual-Function Input 5 INT2 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output Reset Reset 7 X1, X2 Crystal PIN Functions Prom Mode CE Chip Enable ..... InputOE Output Enable ..... Input 1 A0 to A14 Address ..... Input PIN Functions PIN INPUT/OUTPUT Circuits Pin Input/output TypesRemarks a circle P22/PCL OUT IN/OUT Type F B Type M a P00, Reset PIN Functions Unused PIN Treatment Features of Architecture and Memory MAP Data Memory Bank Configuration FB0H FbfhFF0H Fffh Addressing Mode List @HL Data Memory Addressing Modes Bit direct addressing mem.bitBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Stack addressing SUB Push POP RETPush HL POP Push HL Push XA RET Features of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware Operation ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Internal CPU Functions Program Counter PC .... BitsPC1 PC0 Program Memory ROM .... ,920 Words × 8 Bits Program Memory Map Internal CPU Functions Data Memory RAM Data areaGeneral register area Stack area Peripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 Bits Internal CPU Functions Accumulator Accumulators Internal CPU Functions Stack Pointer SP .... Bits Range of 020H to 03FHMOV SP, XA SP4 SP3 SP2 SP1 SP0 Data Saved to Stack Memory IST0 PSW Internal CPU Functions Program Status Word PSW .... Bits Carry flag CYCarry Flag Manipulation Instructions Interrupt Status Flag Indication Content SET1Skip flag SK2, SK1, SK0 Interrupt status flag IST0 Peripheral Hardware Functions PORT0 Digital Input/Output Port Types and Characteristics Csim Poga PO0PO1 INT2 INT0 Configuration of Port PO3 Configuration of Ports 2 Input/Output Mode Setting PM5 Pmgb Digital Input/Output Port Handling Instructions PmgaFech PM5 PM2 Pmgb Bit handling instructions Operations when input mode is set Operations when output mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up Resistors MOV POGA, XA PORT1Fdch PO6 PO3 PO2 PO1 PO0 Digital Input/Output Port Input/Output Timing Data fetch by 2-machine-cycle instructionData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instruction Clock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Function and Operaion Processor clock control register PCCSEL MOV PCC, a FB3H PCC3 PCC2 PCC1 PCC0 PCC System clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry 13 Example of Poor Resonator Connection Circuit 2/2 CPU Clock Setting Use of Variable Minimum Instruction Execution Time FunctionExample 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU Clock Differences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1 Clock Output Circuit Configuration Peripheral Hardware Functions Clock Output CircuitP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Mode Register Clom Clom Clock Output Procedure Examle of Remote Control Application Peripheral Hardware Functions Basic Interval Timer Basic Interval Timer ConfigurationMPX BTM3 BTM2 Basic Intercal Timer Mode Register BTM MOV BTM. aBTM3 BTM Basic Interval Timer Operation From the beginning Examples of Basic Interval Timer Applications MOV BTM,AIebt SEL MOV Operation-halted mode Wire serial I/O modePeripheral Hardware Functions Serial Interface Serial Interface Functions SBI mode serial bus interface mode Serial Interface Configuration Serial Interface Block Diagram Functions Serial operating mode register Csim Serial bus interface control register SbicShift register SIO SO latch Register Functions Serial operating mode register Csim Intcsi control circuitSerial clock control circuit Serial interface operating mode selection bit W Serial clock selection bit WCsie COI WUP CSIM3 CSIM1 Csim Signal from address comparator R Csie MOV CSIM, XA SET1 CsieCsie CSIM3 Csie CSIM1 FE2H Cmdd Reld Cmdt Relt Command trigger bit W Command detection flag RBus release detection flag R Acknowledge trigger bit W Busy enable bit R/W Acknowledge detection flag R SIO CLKBUSY/ACK Error detection See 5.5.6 8 Error detection for detailsSlave address register SVA Slave address detection Register setting Csie C0I WUP CSIM3 CSIM1 Csim 5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System Configuration Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic 29 3-Wire Serial I/O Mode Timing Communication operation Serial Clock Selection and Use in 3-Wire Serial I/O Mode SignalsSerial clock selection Relt Cmdt Data transfer order Start of transfer Wire serial I/O mode applications MOV XA, TdataMOV SIO, XA SCK SO/SB0 MOV XA, Tdata SIO, XA IecsiMOV XA, Tdata XCH XA, SIO MOV RDATA, XA SBI Mode Operation + VDDCPU SB0 SCK SB0 SCK Address/command/data differentiation function Acknowledge signal ACK control functionBusy signal Busy control function SBI functions SBI definition SB0 ACKSB0 C0 ACK Busy SB0 D0 ACK Busy Bus release signal REL Command signal CMDSCK H SCK H SB0 Address 37 Slave Selection by Address Command & data Data Acknowledge signal ACK SCK SB0 ACK Busy signal BUSY, ready signal Ready 100SCK SB0 ACK Busy 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105 RELT, CMDT, Reld & Cmdd Operation Slave 106SIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK 44 Ackt Operation 107 When Acke is set after completion of transfer When Acke = 0 on completion of transferWhen Acke = 1 interval is short 108 When ACK signal is output after 9th SCK clock interval 109SCK SB0 ACK Ackd SCK SB0 Bsye ACK 110 Signals in SBI Mode SCK CmddSB0 ACK Ready SB0 Ready 111 REL CMD Pin configuration Pin Configuration Diagram Address match detection method Use of slave address register SVA113 114 ChapterPeripheral Hardware 50 Command Transmission from Master Device to Slave 115 116 51 Data Transmission from Master Device to Slave Device 52 Data Transmission from Slave Device to Master Device 117 Points to note concerning SBI mode 118 SBI mode application Serial bus configuration119 Description of commands Command types Ii Communication procedure120 Iii Command formats ➀ Read command➁ WRITE, END and Stop commands 121 122 MSMACK Stop ➂ Status command 123Status MSB LSB Reset command ➄ Chgmst command124 Chgmst Iv Error occurrence Errors generated on the slave sideErrors generated on the master side 125 Interrupt Functions 127 Interrupt Functions Interrupt Source Types and Vector Table Interrupt Request Source TypesVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0 Interrupt request flag & interrupt enable flag Interrupt Request Flag Setting SignalExample EI IE0 External interrupt input pin hardware 130 INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise Elimination Interrupt master enable flag IME 132FB4H IM03 FB2H Interrupt status flag IST0 Interrupt Servicing Status133 Interrupt Functions Interrupt Sequence YESIME=1 Interrupt INTxxx generation 136 Interrupt Functions Interrupt Applications Interrupt enabling/disablingEI Iecsi Example using INTBT, INT0 falling edge active, and Intcsi 138CLR1 IRQ0 ➄ Reti 139 EI IE0➂ Intcsi Reti ➃ EI Iecsi Reti Pending interrupt execution 140INT0 Intcsi ➁ Reti Stop mode Halt modeStandby Function Standby Function Standby Mode Setting and Operation States Standby Mode Operation States Standby Function Standby Mode Reset Stop mode reset by Reset inputHalt mode reset by Reset input Halt mode reset by interrupt generation 144 Halt Standby Function Operation After Standby Mode Reset IME = Reset Signal Acceptance Reset at Power-on State of Hardware after Reset 147OFF Architecture and Memory MAP 148 Instruction SET Special Instructions Bit Manipulation InstructionsStack Instructions Example A0 Base Correction Instructions Base correction at additionAddc Adds Addc Instruction SET Instruction SET and ITS Operation Operation identifier and descriptionOperation description legend Description of addressing area field symbols Description of machine cycle field152 Movt XA, @PCXA AddsAddc XOR 154 Instruction Group Instructions155 NOP Description of operation code symbols Instruction SET Operation Code of Each InstructionBit manipulation addressing operation code Iebt Iecsi IE0 IE2 Rorc Not Incs SET CLR SKT Not RET Rets Reti Push POP Halt Stop NOP Instruction SET Instruction Functions and Application Move InstructionsMOV A, #0BH MOV HL, #5FH MOV XA, 20H 160 Loop XCH MOV XCH161 Table Reference Instructions Table data on that162 02FFH Arithmetic and Logic Instructions See section163 Or A, @HL 164 Rorc a 165 Incs reg 166 SKE reg, #n4 167 Carry Flag Operation Instructions 168 Bit Manipuration Instructions 169 SKF mem. bit 170 BR addr 171 Subroutine Stack Control Instructions 172 Push rp 173 Interrupt Control Instructions 174 Input/Output Instructions 175 Halt 176 177 178 Language Processor Prom Writing Tools179 Debugging Tools 180 Development Tool Configuration 181IBM PC/AT 182 183 184 IrqcsPmgb Cmdd Port