NEC PD75P402, PD75402A user manual Contents

					CONTENTS
CHAPTER 1. GENERAL						1
1.1	OUTLINE OF FUNCTIONS					2
1.2	ORDERING INFORMATION AND QUALITY GRADE					3
1.3	DIFFERENCES BETWEEN μPD75402A AND μPD75402, 75P402					4
1.4	BLOCK DIAGRAM					5
1.5	PIN CONFIGURATION					6
	1.5.1	28-Pin Plastic DIP (600 mil), Shrink DIP (400 mil)				6
	1.5.2	44-Pin Plastic QFP ( ■ 10 mm)				8
CHAPTER 2. PIN FUNCTIONS						10
2.1	μPD75402A PIN FUNCTION LIST					11
	2.1.1	Port Pin List				11
	2.1.2	List of Pins Other than Port Pins				12
2.2	NORMAL OPERATING MODE					13
	2.2.1	P00 to P03 (Port 0), P10, P12 (Port 1)				13
	2.2.2	P20 to P23 (Port 2), P30 to P33 (Port 3), P50 to P53 (Port 5), P60 to P63 (Port 6)				14
	2.2.3	SCK, SO/SB0, SI				14
	2.2.4	INT0				14
	2.2.5	INT2				14
	2.2.6	PCL				14
	2.2.7	X1, X2				15
	2.2.8					15
		RESET		................................................................................................................................(Reset)
	2.2.9	VDD				15
	2.2.10	VSS				15
2.3	PROM MODE					16
	2.3.1	A0 to A14 (Address)				16
	2.3.2	O0 to O7 (Data)				16
	2.3.3		(Chip Enable)			16
		CE
	2.3.4					16
		OE	.......................................................................................................................(Output Enable)
	2.3.5	VPP				16
	2.3.6	VDD				16
	2.3.7	VSS				16
2.4	PIN INPUT/OUTPUT CIRCUITS					17
2.5	UNUSED PIN TREATMENT					20
2.6	NOTES ON USE OF P00 PIN AND RESET PIN					20
CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP						21
3.1	DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES					21
	3.1.1	Data Memory Bank Configuration				21
	3.1.2	Data Memory Addressing Modes				24
3.2	MEMORY-MAPPED I/O					28

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