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NEC PD75402A, PD75P402 user manual Major Revisions in This Version

Models: PD75402A PD75P402

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		Major Revisions in This Version

	Section	Description

	P.117	Amendment: Fig. 5-52 “Data Transmission from Slave Device
	P.117	to Master Device”
		to Master Device”

	P.179 to 181	Change: Appendix B “Development Tools”

The mark ★ shows main revised points.

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NEC PD75402A, PD75P402 user manual Major Revisions in This Version

Contents

ΜPD75402A Page Major Revisions in This Version Content to be read carefully Instruction Functions and ApplicationRemarks Latest documents should be used for design purposes, etc Related Documentation Device Related DocumentsDevelopment Tool Related Documents Other Related DocumentsContents Clock Generation Circuit Basic Interval TimerInterrupt Control Circuit Configuration Digital INPUT/OUTPUT PortsStandby Mode Application Standby Mode Setting and Operation StatesStandby Mode Reset Operation After Standby Mode ResetContents of Figures Fig. No Title Table No Title Contents of TablesGeneral FAX PPCECR VCR For details, see Interrupt Functions General Outline of FunctionsGeneral Ordering Information and Quality Grade Ordering InformationQuality Grade VPP PORT6 Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 INT0 Interrupt INT2 ControlVPP NC General PIN ConfigurationSCK SO/SB0Prom mode NC V SS NC P22/PCL 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 P01/SCKA2 NC NC NC NC PIN Functions INT0 ΜPD75402A PIN Function List Port Pin ListSCK SO/SB0SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode4 INT0 ..... Port 1 Dual-Function Input 5 INT2 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output 7 X1, X2 Crystal Reset Reset1 A0 to A14 Address ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input OE Output Enable ..... InputP22/PCL PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types Remarks a circleIN/OUT OUTType F B Type M a PIN Functions Unused PIN Treatment P00, ResetData Memory Bank Configuration Features of Architecture and Memory MAPFB0H FbfhFF0H Fffh @HL Addressing Mode ListData Memory Addressing Modes Bit direct addressing mem.bitBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL Push XA RET Stack addressingSUB Push POP RET Push HL POPApplicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/OΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Internal CPU Functions Program Counter PC .... BitsPC1 PC0 Program Memory Map Program Memory ROM .... ,920 Words × 8 BitsStack area Internal CPU Functions Data Memory RAMData area General register areaPeripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register ConfigurationAccumulators Internal CPU Functions AccumulatorSP4 SP3 SP2 SP1 SP0 Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH MOV SP, XAIST0 PSW Data Saved to Stack MemoryInternal CPU Functions Program Status Word PSW .... Bits Carry flag CYCarry Flag Manipulation Instructions Interrupt status flag IST0 Interrupt Status Flag Indication ContentSET1 Skip flag SK2, SK1, SK0PORT0 Peripheral Hardware FunctionsDigital Input/Output Port Types and Characteristics INT2 INT0 Csim PogaPO0 PO1PO3 Configuration of PortConfiguration of Ports 2 PM5 Pmgb Input/Output Mode SettingDigital Input/Output Port Handling Instructions PmgaFech PM5 PM2 Pmgb Bit handling instructions Operations when input mode is set Operations when output mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each PortMOV POGA, XA PORT1Fdch PO6 PO3 PO2 PO1 PO0 Data latching by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 1-machine-cycle instructionPeripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit ConfigurationMOV PCC, a Clock Generation Circuit Function and OperaionProcessor clock control register PCC SELPCC FB3H PCC3 PCC2 PCC1 PCC012 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit13 Example of Poor Resonator Connection Circuit 2/2 CPU Clock Setting Use of Variable Minimum Instruction Execution Time FunctionExample Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On ResetDifferences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register FormatClock Output Circuit Configuration Peripheral Hardware Functions Clock Output CircuitP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clom Clock Output Mode Register ClomExamle of Remote Control Application Clock Output ProcedureBTM3 BTM2 Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration MPXBTM Basic Intercal Timer Mode Register BTMMOV BTM. a BTM3From the beginning Basic Interval Timer OperationSEL MOV Examples of Basic Interval Timer ApplicationsMOV BTM,A IebtSerial Interface Functions Operation-halted modeWire serial I/O mode Peripheral Hardware Functions Serial InterfaceSerial Interface Configuration SBI mode serial bus interface modeFunctions Serial Interface Block DiagramSO latch Serial operating mode register CsimSerial bus interface control register Sbic Shift register SIORegister Functions Serial operating mode register Csim Intcsi control circuitSerial clock control circuit Serial interface operating mode selection bit W Serial clock selection bit WCsie COI WUP CSIM3 CSIM1 Csim Csie Signal from address comparator RCsie CSIM1 MOV CSIM, XASET1 Csie Csie CSIM3Cmdd Reld Cmdt Relt FE2HAcknowledge trigger bit W Command trigger bit WCommand detection flag R Bus release detection flag RAcknowledge detection flag R Busy enable bit R/WSIO CLKBUSY/ACK Slave address detection Error detectionSee 5.5.6 8 Error detection for details Slave address register SVACsie C0I WUP CSIM3 CSIM1 Csim Register setting28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode OperationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bitCommunication operation 29 3-Wire Serial I/O Mode TimingRelt Cmdt Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Serial clock selectionStart of transfer Data transfer orderSCK SO/SB0 Wire serial I/O mode applicationsMOV XA, Tdata MOV SIO, XAMOV RDATA, XA MOV XA, Tdata SIO, XAIecsi MOV XA, Tdata XCH XA, SIOSB0 SCK SBI Mode Operation+ VDD CPU SB0 SCKSBI functions Address/command/data differentiation functionAcknowledge signal ACK control function Busy signal Busy control functionSB0 D0 ACK Busy SBI definitionSB0 ACK SB0 C0 ACK BusySCK H SB0 Bus release signal RELCommand signal CMD SCK H37 Slave Selection by Address AddressData Command & dataSCK SB0 ACK Acknowledge signal ACKBusy signal BUSY, ready signal Ready 100SCK SB0 ACK Busy 101 102 103 104 105 Serial Clock Selection and Use in SBI ModeSIO SCK RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK SB0 Relt Cmdt Reld Cmdd107 44 Ackt Operation108 When Acke is set after completion of transferWhen Acke = 0 on completion of transfer When Acke = 1 interval is shortSCK SB0 Bsye ACK When ACK signal is output after 9th SCK clock interval109 SCK SB0 ACK AckdSB0 Ready 110 Signals in SBI ModeSCK Cmdd SB0 ACK ReadyREL CMD 111Pin Configuration Diagram Pin configurationAddress match detection method Use of slave address register SVA113 Hardware 114Chapter Peripheral115 50 Command Transmission from Master Device to Slave51 Data Transmission from Master Device to Slave Device 116117 52 Data Transmission from Slave Device to Master Device118 Points to note concerning SBI modeSBI mode application Serial bus configuration119 Description of commands Command types Ii Communication procedure120 121 Iii Command formats➀ Read command ➁ WRITE, END and Stop commands122 MSMACK Stop MSB LSB ➂ Status command123 StatusChgmst Reset command➄ Chgmst command 124125 Iv Error occurrenceErrors generated on the slave side Errors generated on the master sideInterrupt Functions 127 VENT1 Gotobt VENT2 GOTO0 Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VEN T1 GOT OBTIE0 Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal Example EI130 External interrupt input pin hardwareINT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output TimingFB2H Interrupt master enable flag IME132 FB4H IM03Interrupt status flag IST0 Interrupt Servicing Status133 Interrupt Functions Interrupt Sequence YESIME=1 Interrupt INTxxx generation 136 Interrupt Functions Interrupt Applications Interrupt enabling/disablingEI Iecsi ➄ Reti Example using INTBT, INT0 falling edge active, and Intcsi138 CLR1 IRQ0➃ EI Iecsi Reti 139EI IE0 ➂ Intcsi RetiPending interrupt execution 140INT0 Intcsi ➁ Reti Stop mode Halt modeStandby Function Standby Mode Operation States Standby Function Standby Mode Setting and Operation StatesHalt mode reset by interrupt generation Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by Reset inputHalt 144IME = Standby Function Operation After Standby Mode ResetReset at Power-on Reset Signal AcceptanceState of Hardware after Reset 147OFF 148 Architecture and Memory MAPExample A0 Instruction SET Special InstructionsBit Manipulation Instructions Stack InstructionsAdds Addc Base Correction InstructionsBase correction at addition AddcInstruction SET Instruction SET and ITS Operation Operation identifier and descriptionOperation description legend Description of addressing area field symbols Description of machine cycle field152 XOR Movt XA, @PCXAAdds Addc154 NOP Instruction GroupInstructions 155Iebt Iecsi IE0 IE2 Description of operation code symbolsInstruction SET Operation Code of Each Instruction Bit manipulation addressing operation codeSET CLR SKT Not Rorc Not IncsHalt Stop NOP RET Rets Reti Push POPMOV HL, #5FH Instruction SET Instruction Functions and ApplicationMove Instructions MOV A, #0BH160 MOV XA, 20HLoop XCH MOV XCH161 02FFH Table Reference InstructionsTable data on that 162Arithmetic and Logic Instructions See section163 164 Or A, @HL165 Rorc a166 Incs reg167 SKE reg, #n4168 Carry Flag Operation Instructions169 Bit Manipuration Instructions170 SKF mem. bit171 BR addr172 Subroutine Stack Control Instructions173 Push rp174 Interrupt Control Instructions175 Input/Output Instructions176 Halt177 178 Language Processor Prom Writing Tools179 180 Debugging ToolsDevelopment Tool Configuration 181IBM PC/AT 182 183 Port 184Irqcs Pmgb Cmdd