NEC PD75P402 user manual ΜPD75402A I/O Map 1/2

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

Table 3-4 μPD75402A I/O Map (1/2)

Hardware Name (Symbol)

No. of Manipulatable

Bit

Address

Addressing

Manipula-

Remarks

tion

b3

b2

b1

b0

1 Bit

4 Bits

8 Bits

F80H

Stack pointer (SP)

W

Bit 0 is fixed to 0.

11 must always

F85H

Basic interval timer mode register (BTM)

W

be written in

bit 1, 0.

F86H

Basic interval timer (BT)

R

		Manipulation
FB2H	(IME)	by EI. DI instruc-
		tion

FB3H	Processor clock control register (PCC)					W
FB4H	INT0 mode register (IM0)					W		Bit 2 is fixed to 0.
FB8H	0	0	IEBT	IRQBT	R/W	R/W
FBDH	0	0	IECSI	IRQCSI			fmem. bit
					R/W	R/W

FBEH

0

0

IE0

IRQ0

R/W

R/W

FBFH

0

0

IE2

IRQ2

R/W

R/W

FD0H	Clock output mode register (CLOM)	W
FDCH	Pull-up resistor specify register		W
	Group A (POGA)

Remarks 1. IE××× is an interrupt enable flag.

2.IRQ××× is an interrupt request flag.

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