NEC PD75402A, PD75P402 user manual Input/Output Mode Setting, PM5 Pmgb

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Fig. 5-5 Configuration of Port 5

VDD

		Pull-Up Resistors
		(Mask	Option;	μPD75402A
		Only)
	Input Buffer	PM5=0
	M
	P	PM5=1
	X
Bus
Internal			P50
	Latch		P51
	Output		P52
			P53

N-ch

Open-Drain

Output

Buffer

PM5

PMGB

Bit 5

5.1.2Input/Output Mode Setting

The input/output mode for each input/output port is set by a port mode register as shown in Fig. 5-6. For port 3, input/output can be specified bit by bit by port mode register group A (PMGA). Input/output is specified in 4-bit units by PMGB for ports 2 and 5, and by PMGA for port 6.

Each port operates as an input port when the corresponding port mode register bit is “0”, and as an output port when “1”.

Since, when output mode is selected by setting the port mode register, the output latch contents are simulta- neously output to the output pin, the output latch contents must be overwritten in advance with the required value before output mode is set.

Port mode register group A and B are each set by an 8-bit memory handling instruction.

With a RESET input, all bits of each port mode register are cleared to zero, and thus the output buffer is turned off and all ports are set to input mode.

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