NEC PD75P402, PD75402A user manual Serial Clock Selection and Use in SBI Mode, 105

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Busy enable bit (R/W)

BSYE

➀Disablin of automatic busy signal output

0➁ Busy signal output is stopped in synchronization with the fall of SCK immediately after execution ofthe clearing instruction.

1	The busy signal is output in synchronization with the fall or SCK following the
	acknowledge signal.

(4) Serial clock selection

Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the following clocks can be selected.

Table 5-7 Serial Clock Selection and Use (in SBI Mode)

Mode		Serial Clock		Possible Timing for Shift
Register
				Register R/W and Serial	Use
CSIM 1	Source		Serial Clock	Transfer Start
			Masking
0	External		Automatically	Possible only when serial transfer	Slave CPU
			masked at end of
	SCK			is halted* or when SCK is high.
			8-bit data
1	fXX/24		transfer.	Possible only when serial transfer	Medium-speed
				is halted* or when SCK is high.	serial transfer

*“When serial transfer is halted” means in the operation- halted mode, or when the serial clock is masked after an 8-bit transfer.

When the internal system clock is selected SCK stops at 8 pulses internally, but externally the count continues until the slave is in the ready state.

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