CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Fig. 5-4 Configuration of Ports 2 and 6

VDD

Pull-up

Resistors

POGA

P-ch

Bit m

 

 

 

 

POm

 

Input Buffer

 

 

 

 

 

 

PMm = 0

 

 

 

M

 

 

 

 

P

PMm = 1

 

 

 

X

 

 

 

 

Bus

 

 

 

P m 0

Internal

 

 

 

Latch

 

 

P m 1

 

 

 

 

Output

 

 

P m 2

 

 

 

 

 

 

 

 

P m 3

 

 

 

 

Output

 

PM2/

*

 

Buffer

 

 

 

PM60 to 63

PMGB Bit 2, PMGA bits 4 to 7

*Input/output mode specification is performed by bit 2 (PM2) of PMGB for port 2 and by bits 4 to 7 (PM60 to 63) of PMGA for port 6.

Remarks m = 2 or 6

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NEC PD75P402, PD75402A user manual Configuration of Ports 2