Busy signal BUSY, ready signal Ready, 100

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(f)Busy signal (BUSY), ready signal (READY)

The busy signal notifies the master that a slave is preparing for data transmission/reception. The ready signal notifies the master that a slave is ready for data transmission/reception.

Fig. 5-41 Busy Signal & Ready Signal

SCK

SB0

ACK

BUSY

READY

With the SBI a slave reports its busy status to the master by driving the SB0 line low.

The busy signal is output following the acknowledge signal output by the master or slave. Busy signal setting/release is performed in synchronization with the fall of SCK. When the busy signal is released the master automatically terminates output of the SCK serial clock.

When the busy signal is released and the ready signal sate is entered the master can start the next transfer.

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NEC PD75402A, PD75P402 user manual Busy signal BUSY, ready signal Ready, 100, SCK SB0 ACK Busy

Contents

ΜPD75402A Page Major Revisions in This Version Content to be read carefully Instruction Functions and ApplicationRemarks Latest documents should be used for design purposes, etc Related Documentation Device Related DocumentsDevelopment Tool Related Documents Other Related Documents Contents Clock Generation Circuit Basic Interval TimerInterrupt Control Circuit Configuration Digital INPUT/OUTPUT Ports Standby Mode Application Standby Mode Setting and Operation StatesStandby Mode Reset Operation After Standby Mode Reset Contents of Figures Fig. No Title Table No Title Contents of Tables General FAX PPCECR VCR For details, see Interrupt Functions General Outline of Functions General Ordering Information and Quality Grade Ordering InformationQuality Grade VPP PORT6 Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 INT0 Interrupt INT2 Control VPP NC General PIN ConfigurationSCK SO/SB0 Prom mode NC V SS NC P22/PCL 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 P01/SCK A2 NC NC NC NC PIN Functions INT0 ΜPD75402A PIN Function List Port Pin ListSCK SO/SB0 SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode 4 INT0 ..... Port 1 Dual-Function Input 5 INT2 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output 7 X1, X2 Crystal Reset Reset 1 A0 to A14 Address ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input OE Output Enable ..... Input P22/PCL PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types Remarks a circle IN/OUT OUT Type F B Type M a PIN Functions Unused PIN Treatment P00, Reset Data Memory Bank Configuration Features of Architecture and Memory MAP FB0H FbfhFF0H Fffh @HL Addressing Mode List Data Memory Addressing Modes Bit direct addressing mem.bitBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL Push XA RET Stack addressingSUB Push POP RET Push HL POP Applicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/O ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Internal CPU Functions Program Counter PC .... BitsPC1 PC0 Program Memory Map Program Memory ROM .... ,920 Words × 8 Bits Stack area Internal CPU Functions Data Memory RAMData area General register area Peripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register Configuration Accumulators Internal CPU Functions Accumulator SP4 SP3 SP2 SP1 SP0 Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH MOV SP, XA IST0 PSW Data Saved to Stack Memory Internal CPU Functions Program Status Word PSW .... Bits Carry flag CYCarry Flag Manipulation Instructions Interrupt status flag IST0 Interrupt Status Flag Indication ContentSET1 Skip flag SK2, SK1, SK0 PORT0 Peripheral Hardware Functions Digital Input/Output Port Types and Characteristics INT2 INT0 Csim PogaPO0 PO1 PO3 Configuration of Port Configuration of Ports 2 PM5 Pmgb Input/Output Mode Setting Digital Input/Output Port Handling Instructions PmgaFech PM5 PM2 Pmgb Bit handling instructions Operations when input mode is set Operations when output mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each Port MOV POGA, XA PORT1Fdch PO6 PO3 PO2 PO1 PO0 Data latching by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 1-machine-cycle instruction Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Configuration MOV PCC, a Clock Generation Circuit Function and OperaionProcessor clock control register PCC SEL PCC FB3H PCC3 PCC2 PCC1 PCC0 12 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit 13 Example of Poor Resonator Connection Circuit 2/2 CPU Clock Setting Use of Variable Minimum Instruction Execution Time FunctionExample Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On Reset Differences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register Format Clock Output Circuit Configuration Peripheral Hardware Functions Clock Output CircuitP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clom Clock Output Mode Register Clom Examle of Remote Control Application Clock Output Procedure BTM3 BTM2 Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration MPX BTM Basic Intercal Timer Mode Register BTMMOV BTM. a BTM3 From the beginning Basic Interval Timer Operation SEL MOV Examples of Basic Interval Timer ApplicationsMOV BTM,A Iebt Serial Interface Functions Operation-halted modeWire serial I/O mode Peripheral Hardware Functions Serial Interface Serial Interface Configuration SBI mode serial bus interface mode Functions Serial Interface Block Diagram SO latch Serial operating mode register CsimSerial bus interface control register Sbic Shift register SIO Register Functions Serial operating mode register Csim Intcsi control circuitSerial clock control circuit Serial interface operating mode selection bit W Serial clock selection bit WCsie COI WUP CSIM3 CSIM1 Csim Csie Signal from address comparator R Csie CSIM1 MOV CSIM, XASET1 Csie Csie CSIM3 Cmdd Reld Cmdt Relt FE2H Acknowledge trigger bit W Command trigger bit WCommand detection flag R Bus release detection flag R Acknowledge detection flag R Busy enable bit R/W SIO CLKBUSY/ACK Slave address detection Error detectionSee 5.5.6 8 Error detection for details Slave address register SVA Csie C0I WUP CSIM3 CSIM1 Csim Register setting 28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode Operation Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bit Communication operation 29 3-Wire Serial I/O Mode Timing Relt Cmdt Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Serial clock selection Start of transfer Data transfer order SCK SO/SB0 Wire serial I/O mode applicationsMOV XA, Tdata MOV SIO, XA MOV RDATA, XA MOV XA, Tdata SIO, XAIecsi MOV XA, Tdata XCH XA, SIO SB0 SCK SBI Mode Operation+ VDD CPU SB0 SCK SBI functions Address/command/data differentiation functionAcknowledge signal ACK control function Busy signal Busy control function SB0 D0 ACK Busy SBI definitionSB0 ACK SB0 C0 ACK Busy SCK H SB0 Bus release signal RELCommand signal CMD SCK H 37 Slave Selection by Address Address Data Command & data SCK SB0 ACK Acknowledge signal ACK Busy signal BUSY, ready signal Ready 100SCK SB0 ACK Busy 101 102 103 104 105 Serial Clock Selection and Use in SBI Mode SIO SCK RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK SB0 Relt Cmdt Reld Cmdd 107 44 Ackt Operation 108 When Acke is set after completion of transferWhen Acke = 0 on completion of transfer When Acke = 1 interval is short SCK SB0 Bsye ACK When ACK signal is output after 9th SCK clock interval109 SCK SB0 ACK Ackd SB0 Ready 110 Signals in SBI ModeSCK Cmdd SB0 ACK Ready REL CMD 111 Pin Configuration Diagram Pin configuration Address match detection method Use of slave address register SVA113 Hardware 114Chapter Peripheral 115 50 Command Transmission from Master Device to Slave 51 Data Transmission from Master Device to Slave Device 116 117 52 Data Transmission from Slave Device to Master Device 118 Points to note concerning SBI mode SBI mode application Serial bus configuration119 Description of commands Command types Ii Communication procedure120 121 Iii Command formats➀ Read command ➁ WRITE, END and Stop commands 122 MSMACK Stop MSB LSB ➂ Status command123 Status Chgmst Reset command➄ Chgmst command 124 125 Iv Error occurrenceErrors generated on the slave side Errors generated on the master side Interrupt Functions 127 VENT1 Gotobt VENT2 GOTO0 Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VEN T1 GOT OBT IE0 Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal Example EI 130 External interrupt input pin hardware INT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output Timing FB2H Interrupt master enable flag IME132 FB4H IM03 Interrupt status flag IST0 Interrupt Servicing Status133 Interrupt Functions Interrupt Sequence YESIME=1 Interrupt INTxxx generation 136 Interrupt Functions Interrupt Applications Interrupt enabling/disablingEI Iecsi ➄ Reti Example using INTBT, INT0 falling edge active, and Intcsi138 CLR1 IRQ0 ➃ EI Iecsi Reti 139EI IE0 ➂ Intcsi Reti Pending interrupt execution 140INT0 Intcsi ➁ Reti Stop mode Halt modeStandby Function Standby Mode Operation States Standby Function Standby Mode Setting and Operation States Halt mode reset by interrupt generation Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by Reset input Halt 144 IME = Standby Function Operation After Standby Mode Reset Reset at Power-on Reset Signal Acceptance State of Hardware after Reset 147OFF 148 Architecture and Memory MAP Example A0 Instruction SET Special InstructionsBit Manipulation Instructions Stack Instructions Adds Addc Base Correction InstructionsBase correction at addition Addc Instruction SET Instruction SET and ITS Operation Operation identifier and descriptionOperation description legend Description of addressing area field symbols Description of machine cycle field152 XOR Movt XA, @PCXAAdds Addc 154 NOP Instruction GroupInstructions 155 Iebt Iecsi IE0 IE2 Description of operation code symbolsInstruction SET Operation Code of Each Instruction Bit manipulation addressing operation code SET CLR SKT Not Rorc Not Incs Halt Stop NOP RET Rets Reti Push POP MOV HL, #5FH Instruction SET Instruction Functions and ApplicationMove Instructions MOV A, #0BH 160 MOV XA, 20H Loop XCH MOV XCH161 02FFH Table Reference InstructionsTable data on that 162 Arithmetic and Logic Instructions See section163 164 Or A, @HL 165 Rorc a 166 Incs reg 167 SKE reg, #n4 168 Carry Flag Operation Instructions 169 Bit Manipuration Instructions 170 SKF mem. bit 171 BR addr 172 Subroutine Stack Control Instructions 173 Push rp 174 Interrupt Control Instructions 175 Input/Output Instructions 176 Halt 177 178 Language Processor Prom Writing Tools179 180 Debugging Tools Development Tool Configuration 181IBM PC/AT 182 183 Port 184Irqcs Pmgb Cmdd