NEC PD75P402, PD75402A user manual Sio, Clk, Busy/Ack

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(3) Shift register (SIO)

The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel- to-serial conversion and performs serial transmission/reception (shift operations) in synchronization with the serial clock.

A serial transfer is started by writing data to SIO.

In transmission, the data written to SIO is output to the serial output (SO) or the serial data bus (SB0). In reception, data is read into SIO from the serial input (SI) or SB0.

SIO can be read or written to by an 8-bit manipulation instruction.

If RESET is input during its operation, the value of SIO is indeterminate. If RESET is input in the standby mode, the value of SIO is retained.

The shift operation stops after transmission/reception of 8 bits.

Fig. 5-27 Configuration Around Shift Register

Internal Bus	Address			RELT
	Comparator			CMDT
Shift Register		SET	CLR	SO Latch
(SIO)
P02/SO	D		Q
/SB0
			CLK
Shift Clock			BUSY/ACK
N-ch Open-Drain Output

SIO reading and the start of a serial transfer (write) are possible at the following times:

•When the serial interface operation enable/disable bit (CSIE) = 1, except when CSIE is set to “1” after data has been written into the shift register.

•When the serial clock has been masked agter an 8-bit serial transfer.

•When SCK is high.

Ensure that SCK is high when data is written to or read from the SIO register.

In the SBI mode data bus configuration, input pins and output pins have dual functions. Output pins have an N- ch open-drain configuration. Therefore, in a device in which reception is about to be performed, FFH should be set in the SIO register.

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