Manuals / NEC / Computer Equipment / Computer Hardware

NEC PD75402A, PD75P402 user manual Acknowledge detection flag R, Busy enable bit R/W

Models: PD75402A PD75P402

1 195

Download 195 pages 45.34 Kb

Page 91

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3)

Acknowledge enable bit (R/W)

ACKE


0	Disables automatic output of the acknowledge signal (ACK) (outpt by ACKT is
0	possibel).
	possibel).


	When set before end of transfer	ACK is output is synchronization with the 9th
	When set before end of transfer	SCK clock cycle.
1		SCK clock cycle.


	When set after end of transfer	ACK is output in synchronization with SCK
	When set after end of transfer	immediately after execution of the setting
		instruction.

Acknowledge detection flag (R)

ACKD

	Clearing Conditions (ACKD = 0)	Setting Condition (ACKD = 1)

➀	When a transfer is started
➀	When a transfer is started	When the acknowledge signal (ACK) is de-
➁	When RESET is input	tected (Synchronized with rise of SCK)

Busy enable bit (R/W)

BSYE

➀Disablin of automatic busy signal output

0➁ Busy signal output is stopped in synchronization with the fall of SCK immediately after execution ofthe clearing instruction.

	1	The busy signal is output in synchronization with the fall or SCK following the
	1	acknowledge signal.
		acknowledge signal.

Example 1. To output the command signal.

SET1 CMDT

2.To test RELD and CMDD, and perform different processing according to the type of receive data. This interrupt routine is only performed when WUP = 1 and there is an address match.

SKF	RELD	;	Test RELD
BR	!ADRS
SKT	CMDD	;	Test CMDD
BR	!DATA

CMD	:	;	Command interpretation
DATA	:	;	Data processing
ADRS	:	;	Address decoding

80

Image 91

NEC PD75402A, PD75P402 user manual Acknowledge detection flag R, Busy enable bit R/W

Contents

ΜPD75402A Page Major Revisions in This Version Instruction Functions and Application Content to be read carefullyRemarks Latest documents should be used for design purposes, etc Related Documentation Device Related DocumentsDevelopment Tool Related Documents Other Related DocumentsContents Clock Generation Circuit Basic Interval TimerInterrupt Control Circuit Configuration Digital INPUT/OUTPUT PortsStandby Mode Application Standby Mode Setting and Operation StatesStandby Mode Reset Operation After Standby Mode ResetContents of Figures Fig. No Title Table No Title Contents of TablesFAX PPC GeneralECR VCR For details, see Interrupt Functions General Outline of FunctionsOrdering Information General Ordering Information and Quality GradeQuality Grade VPP PORT6 Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 INT0 Interrupt INT2 ControlVPP NC General PIN ConfigurationSCK SO/SB0Prom mode NC V SS NC P22/PCL 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 P01/SCKA2 NC NC NC NC PIN Functions INT0 ΜPD75402A PIN Function List Port Pin ListSCK SO/SB0SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode5 INT2 ..... Port 1 Dual-Function Input 4 INT0 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output 7 X1, X2 Crystal Reset Reset1 A0 to A14 Address ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input OE Output Enable ..... InputP22/PCL PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types Remarks a circleIN/OUT OUTType F B Type M a PIN Functions Unused PIN Treatment P00, ResetData Memory Bank Configuration Features of Architecture and Memory MAPFbfh FB0HFF0H Fffh @HL Addressing Mode ListBit direct addressing mem.bit Data Memory Addressing ModesBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL Push XA RET Stack addressingSUB Push POP RET Push HL POPApplicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/OΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Program Counter PC .... Bits Internal CPU FunctionsPC1 PC0 Program Memory Map Program Memory ROM .... ,920 Words × 8 BitsStack area Internal CPU Functions Data Memory RAMData area General register areaPeripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register ConfigurationAccumulators Internal CPU Functions AccumulatorSP4 SP3 SP2 SP1 SP0 Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH MOV SP, XAIST0 PSW Data Saved to Stack MemoryCarry flag CY Internal CPU Functions Program Status Word PSW .... BitsCarry Flag Manipulation Instructions Interrupt status flag IST0 Interrupt Status Flag Indication ContentSET1 Skip flag SK2, SK1, SK0PORT0 Peripheral Hardware FunctionsDigital Input/Output Port Types and Characteristics INT2 INT0 Csim PogaPO0 PO1PO3 Configuration of PortConfiguration of Ports 2 PM5 Pmgb Input/Output Mode SettingPmga Digital Input/Output Port Handling InstructionsFech PM5 PM2 Pmgb Bit handling instructions Operations when output mode is set Operations when input mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each PortPORT1 MOV POGA, XAFdch PO6 PO3 PO2 PO1 PO0 Data latching by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 1-machine-cycle instructionPeripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit ConfigurationMOV PCC, a Clock Generation Circuit Function and OperaionProcessor clock control register PCC SELPCC FB3H PCC3 PCC2 PCC1 PCC012 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit13 Example of Poor Resonator Connection Circuit 2/2 Use of Variable Minimum Instruction Execution Time Function CPU Clock SettingExample Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On ResetDifferences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register FormatPeripheral Hardware Functions Clock Output Circuit Clock Output Circuit ConfigurationP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clom Clock Output Mode Register ClomExamle of Remote Control Application Clock Output ProcedureBTM3 BTM2 Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration MPXBTM Basic Intercal Timer Mode Register BTMMOV BTM. a BTM3From the beginning Basic Interval Timer OperationSEL MOV Examples of Basic Interval Timer ApplicationsMOV BTM,A IebtSerial Interface Functions Operation-halted modeWire serial I/O mode Peripheral Hardware Functions Serial InterfaceSerial Interface Configuration SBI mode serial bus interface modeFunctions Serial Interface Block DiagramSO latch Serial operating mode register CsimSerial bus interface control register Sbic Shift register SIOIntcsi control circuit Register Functions Serial operating mode register CsimSerial clock control circuit Serial clock selection bit W Serial interface operating mode selection bit WCsie COI WUP CSIM3 CSIM1 Csim Csie Signal from address comparator RCsie CSIM1 MOV CSIM, XASET1 Csie Csie CSIM3Cmdd Reld Cmdt Relt FE2HAcknowledge trigger bit W Command trigger bit WCommand detection flag R Bus release detection flag RAcknowledge detection flag R Busy enable bit R/WCLK SIOBUSY/ACK Slave address detection Error detectionSee 5.5.6 8 Error detection for details Slave address register SVACsie C0I WUP CSIM3 CSIM1 Csim Register setting28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode OperationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bitCommunication operation 29 3-Wire Serial I/O Mode TimingRelt Cmdt Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Serial clock selectionStart of transfer Data transfer orderSCK SO/SB0 Wire serial I/O mode applicationsMOV XA, Tdata MOV SIO, XAMOV RDATA, XA MOV XA, Tdata SIO, XAIecsi MOV XA, Tdata XCH XA, SIOSB0 SCK SBI Mode Operation+ VDD CPU SB0 SCKSBI functions Address/command/data differentiation functionAcknowledge signal ACK control function Busy signal Busy control functionSB0 D0 ACK Busy SBI definitionSB0 ACK SB0 C0 ACK BusySCK H SB0 Bus release signal RELCommand signal CMD SCK H37 Slave Selection by Address AddressData Command & dataSCK SB0 ACK Acknowledge signal ACK100 Busy signal BUSY, ready signal ReadySCK SB0 ACK Busy 101 102 103 104 105 Serial Clock Selection and Use in SBI ModeSIO SCK RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK SB0 Relt Cmdt Reld Cmdd107 44 Ackt Operation108 When Acke is set after completion of transferWhen Acke = 0 on completion of transfer When Acke = 1 interval is shortSCK SB0 Bsye ACK When ACK signal is output after 9th SCK clock interval109 SCK SB0 ACK AckdSB0 Ready 110 Signals in SBI ModeSCK Cmdd SB0 ACK ReadyREL CMD 111Pin Configuration Diagram Pin configurationUse of slave address register SVA Address match detection method113 Hardware 114Chapter Peripheral115 50 Command Transmission from Master Device to Slave51 Data Transmission from Master Device to Slave Device 116117 52 Data Transmission from Slave Device to Master Device118 Points to note concerning SBI modeSerial bus configuration SBI mode application119 Ii Communication procedure Description of commands Command types120 121 Iii Command formats➀ Read command ➁ WRITE, END and Stop commandsMSM 122ACK Stop MSB LSB ➂ Status command123 StatusChgmst Reset command➄ Chgmst command 124125 Iv Error occurrenceErrors generated on the slave side Errors generated on the master sideInterrupt Functions 127 VENT1 Gotobt VENT2 GOTO0 Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VEN T1 GOT OBTIE0 Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal Example EI130 External interrupt input pin hardwareINT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output TimingFB2H Interrupt master enable flag IME132 FB4H IM03IST0 Interrupt Servicing Status Interrupt status flag133 YES Interrupt Functions Interrupt SequenceIME=1 Interrupt INTxxx generation 136 Interrupt enabling/disabling Interrupt Functions Interrupt ApplicationsEI Iecsi ➄ Reti Example using INTBT, INT0 falling edge active, and Intcsi138 CLR1 IRQ0➃ EI Iecsi Reti 139EI IE0 ➂ Intcsi Reti140 Pending interrupt executionINT0 Intcsi ➁ Reti Halt mode Stop modeStandby Function Standby Mode Operation States Standby Function Standby Mode Setting and Operation StatesHalt mode reset by interrupt generation Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by Reset inputHalt 144IME = Standby Function Operation After Standby Mode ResetReset at Power-on Reset Signal Acceptance147 State of Hardware after ResetOFF 148 Architecture and Memory MAPExample A0 Instruction SET Special InstructionsBit Manipulation Instructions Stack InstructionsAdds Addc Base Correction InstructionsBase correction at addition AddcOperation identifier and description Instruction SET Instruction SET and ITS OperationOperation description legend Description of machine cycle field Description of addressing area field symbols152 XOR Movt XA, @PCXAAdds Addc154 NOP Instruction GroupInstructions 155Iebt Iecsi IE0 IE2 Description of operation code symbolsInstruction SET Operation Code of Each Instruction Bit manipulation addressing operation codeSET CLR SKT Not Rorc Not IncsHalt Stop NOP RET Rets Reti Push POPMOV HL, #5FH Instruction SET Instruction Functions and ApplicationMove Instructions MOV A, #0BH160 MOV XA, 20HMOV XCH Loop XCH161 02FFH Table Reference InstructionsTable data on that 162See section Arithmetic and Logic Instructions163 164 Or A, @HL165 Rorc a166 Incs reg167 SKE reg, #n4168 Carry Flag Operation Instructions169 Bit Manipuration Instructions170 SKF mem. bit171 BR addr172 Subroutine Stack Control Instructions173 Push rp174 Interrupt Control Instructions175 Input/Output Instructions176 Halt177 178 Prom Writing Tools Language Processor179 180 Debugging Tools181 Development Tool ConfigurationIBM PC/AT 182 183 Port 184Irqcs Pmgb Cmdd