Bus release signal REL, Command signal CMD, Sck H

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(a) Bus release signal (REL)

The bus release signal indicates that the SB0 line has changed from low to high when the SCK line is high (when the serial clock is not being output). This signal is output by the master.

Fig. 5-34 Bus Release Signal

SCK “H”

SB0

The bus release signal indicates that the master is about to send an address to a slave. Slaves incorporate hardware to detect the bus release signal.

(b) Command signal (CMD)

The command signal indicates that the SB0 line has changed from high to low when the SCK line is high (when the serial clock is not being output). This signal is output by the master.

Fig. 5-35 Command Signal

SCK “H”

SB0

Slave incorporate hardware to detect the command signal.

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Image 107

NEC PD75402A, PD75P402 user manual Bus release signal REL, Command signal CMD, Sck H, SCK H SB0

Contents

ΜPD75402A Page Major Revisions in This Version Remarks Content to be read carefullyInstruction Functions and Application Latest documents should be used for design purposes, etc Related Documentation Device Related DocumentsDevelopment Tool Related Documents Other Related Documents Contents Clock Generation Circuit Basic Interval TimerInterrupt Control Circuit Configuration Digital INPUT/OUTPUT Ports Standby Mode Application Standby Mode Setting and Operation StatesStandby Mode Reset Operation After Standby Mode Reset Contents of Figures Fig. No Title Table No Title Contents of Tables ECR VCR GeneralFAX PPC For details, see Interrupt Functions General Outline of Functions Quality Grade General Ordering Information and Quality GradeOrdering Information VPP PORT6 Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 INT0 Interrupt INT2 Control VPP NC General PIN ConfigurationSCK SO/SB0 Prom mode NC V SS NC P22/PCL 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 P01/SCK A2 NC NC NC NC PIN Functions INT0 ΜPD75402A PIN Function List Port Pin ListSCK SO/SB0 SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode PCL ..... Port 2 Dual-Function Output 4 INT0 ..... Port 1 Dual-Function Input5 INT2 ..... Port 1 Dual-Function Input 7 X1, X2 Crystal Reset Reset 1 A0 to A14 Address ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input OE Output Enable ..... Input P22/PCL PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types Remarks a circle IN/OUT OUT Type F B Type M a PIN Functions Unused PIN Treatment P00, Reset Data Memory Bank Configuration Features of Architecture and Memory MAP FF0H Fffh FB0HFbfh @HL Addressing Mode List Bit direct addressing mem Data Memory Addressing ModesBit direct addressing mem.bit Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL Push XA RET Stack addressingSUB Push POP RET Push HL POP Applicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/O ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 PC1 PC0 Internal CPU FunctionsProgram Counter PC .... Bits Program Memory Map Program Memory ROM .... ,920 Words × 8 Bits Stack area Internal CPU Functions Data Memory RAMData area General register area Peripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register Configuration Accumulators Internal CPU Functions Accumulator SP4 SP3 SP2 SP1 SP0 Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH MOV SP, XA IST0 PSW Data Saved to Stack Memory Carry Flag Manipulation Instructions Internal CPU Functions Program Status Word PSW .... BitsCarry flag CY Interrupt status flag IST0 Interrupt Status Flag Indication ContentSET1 Skip flag SK2, SK1, SK0 PORT0 Peripheral Hardware Functions Digital Input/Output Port Types and Characteristics INT2 INT0 Csim PogaPO0 PO1 PO3 Configuration of Port Configuration of Ports 2 PM5 Pmgb Input/Output Mode Setting Fech PM5 PM2 Pmgb Digital Input/Output Port Handling InstructionsPmga Bit handling instructions Digital Input/Output Port Operations Operations when input mode is setOperations when output mode is set Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each Port Fdch PO6 PO3 PO2 PO1 PO0 MOV POGA, XAPORT1 Data latching by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 1-machine-cycle instruction Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Configuration MOV PCC, a Clock Generation Circuit Function and OperaionProcessor clock control register PCC SEL PCC FB3H PCC3 PCC2 PCC1 PCC0 12 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit 13 Example of Poor Resonator Connection Circuit 2/2 Example CPU Clock SettingUse of Variable Minimum Instruction Execution Time Function Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On Reset Differences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register Format P22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Circuit ConfigurationPeripheral Hardware Functions Clock Output Circuit Clom Clock Output Mode Register Clom Examle of Remote Control Application Clock Output Procedure BTM3 BTM2 Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration MPX BTM Basic Intercal Timer Mode Register BTMMOV BTM. a BTM3 From the beginning Basic Interval Timer Operation SEL MOV Examples of Basic Interval Timer ApplicationsMOV BTM,A Iebt Serial Interface Functions Operation-halted modeWire serial I/O mode Peripheral Hardware Functions Serial Interface Serial Interface Configuration SBI mode serial bus interface mode Functions Serial Interface Block Diagram SO latch Serial operating mode register CsimSerial bus interface control register Sbic Shift register SIO Serial clock control circuit Register Functions Serial operating mode register CsimIntcsi control circuit Csie COI WUP CSIM3 CSIM1 Csim Serial interface operating mode selection bit WSerial clock selection bit W Csie Signal from address comparator R Csie CSIM1 MOV CSIM, XASET1 Csie Csie CSIM3 Cmdd Reld Cmdt Relt FE2H Acknowledge trigger bit W Command trigger bit WCommand detection flag R Bus release detection flag R Acknowledge detection flag R Busy enable bit R/W BUSY/ACK SIOCLK Slave address detection Error detectionSee 5.5.6 8 Error detection for details Slave address register SVA Csie C0I WUP CSIM3 CSIM1 Csim Register setting 28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode Operation Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bit Communication operation 29 3-Wire Serial I/O Mode Timing Relt Cmdt Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Serial clock selection Start of transfer Data transfer order SCK SO/SB0 Wire serial I/O mode applicationsMOV XA, Tdata MOV SIO, XA MOV RDATA, XA MOV XA, Tdata SIO, XAIecsi MOV XA, Tdata XCH XA, SIO SB0 SCK SBI Mode Operation+ VDD CPU SB0 SCK SBI functions Address/command/data differentiation functionAcknowledge signal ACK control function Busy signal Busy control function SB0 D0 ACK Busy SBI definitionSB0 ACK SB0 C0 ACK Busy SCK H SB0 Bus release signal RELCommand signal CMD SCK H 37 Slave Selection by Address Address Data Command & data SCK SB0 ACK Acknowledge signal ACK SCK SB0 ACK Busy Busy signal BUSY, ready signal Ready100 101 102 103 104 105 Serial Clock Selection and Use in SBI Mode SIO SCK RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK SB0 Relt Cmdt Reld Cmdd 107 44 Ackt Operation 108 When Acke is set after completion of transferWhen Acke = 0 on completion of transfer When Acke = 1 interval is short SCK SB0 Bsye ACK When ACK signal is output after 9th SCK clock interval109 SCK SB0 ACK Ackd SB0 Ready 110 Signals in SBI ModeSCK Cmdd SB0 ACK Ready REL CMD 111 Pin Configuration Diagram Pin configuration 113 Address match detection methodUse of slave address register SVA Hardware 114Chapter Peripheral 115 50 Command Transmission from Master Device to Slave 51 Data Transmission from Master Device to Slave Device 116 117 52 Data Transmission from Slave Device to Master Device 118 Points to note concerning SBI mode 119 SBI mode applicationSerial bus configuration 120 Description of commands Command typesIi Communication procedure 121 Iii Command formats➀ Read command ➁ WRITE, END and Stop commands ACK Stop 122MSM MSB LSB ➂ Status command123 Status Chgmst Reset command➄ Chgmst command 124 125 Iv Error occurrenceErrors generated on the slave side Errors generated on the master side Interrupt Functions 127 VENT1 Gotobt VENT2 GOTO0 Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VEN T1 GOT OBT IE0 Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal Example EI 130 External interrupt input pin hardware INT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output Timing FB2H Interrupt master enable flag IME132 FB4H IM03 133 Interrupt status flagIST0 Interrupt Servicing Status IME=1 Interrupt Functions Interrupt SequenceYES Interrupt INTxxx generation 136 EI Iecsi Interrupt Functions Interrupt ApplicationsInterrupt enabling/disabling ➄ Reti Example using INTBT, INT0 falling edge active, and Intcsi138 CLR1 IRQ0 ➃ EI Iecsi Reti 139EI IE0 ➂ Intcsi Reti INT0 Intcsi ➁ Reti Pending interrupt execution140 Standby Function Stop modeHalt mode Standby Mode Operation States Standby Function Standby Mode Setting and Operation States Halt mode reset by interrupt generation Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by Reset input Halt 144 IME = Standby Function Operation After Standby Mode Reset Reset at Power-on Reset Signal Acceptance OFF State of Hardware after Reset147 148 Architecture and Memory MAP Example A0 Instruction SET Special InstructionsBit Manipulation Instructions Stack Instructions Adds Addc Base Correction InstructionsBase correction at addition Addc Operation description legend Instruction SET Instruction SET and ITS OperationOperation identifier and description 152 Description of addressing area field symbolsDescription of machine cycle field XOR Movt XA, @PCXAAdds Addc 154 NOP Instruction GroupInstructions 155 Iebt Iecsi IE0 IE2 Description of operation code symbolsInstruction SET Operation Code of Each Instruction Bit manipulation addressing operation code SET CLR SKT Not Rorc Not Incs Halt Stop NOP RET Rets Reti Push POP MOV HL, #5FH Instruction SET Instruction Functions and ApplicationMove Instructions MOV A, #0BH 160 MOV XA, 20H 161 Loop XCHMOV XCH 02FFH Table Reference InstructionsTable data on that 162 163 Arithmetic and Logic InstructionsSee section 164 Or A, @HL 165 Rorc a 166 Incs reg 167 SKE reg, #n4 168 Carry Flag Operation Instructions 169 Bit Manipuration Instructions 170 SKF mem. bit 171 BR addr 172 Subroutine Stack Control Instructions 173 Push rp 174 Interrupt Control Instructions 175 Input/Output Instructions 176 Halt 177 178 179 Language ProcessorProm Writing Tools 180 Debugging Tools IBM PC/AT Development Tool Configuration181 182 183 Port 184Irqcs Pmgb Cmdd