NEC PD75402A, PD75P402 - page 35

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

24

3.1.2 Data Memory Addressing Modes

In the

µ

PD75402A, the 6 types of addressing modes listed on Table 3-2 are available for the data memory space

for efficient addressing per the bit length of the data to be processed.

Also in the

µ

PD75402A, the memory bank to be accessed is fixed by the addressing mode unlike in other products

of the 75X series. So programming is possible without caring about memory bank switching.

(1) 1-bit direct addressing (mem.bit)

An addressing mode to specify each bit of the whole data memory space directly by the instruction’s operand.

The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3FH and MB = 15

if it is 80H to FFH. Consequently, all the bits in both the static RAM area of 000H to 03FH and the peripheral hardware

area of FF0H to FFFH are addressable. In the peripheral hardware area, however, the bits capable of 1-bit

manipulation are limited (see Table 3-2).

This addressing mode is applied to the 4 instructions of the bit set and reset instructions (SET1, CLR1) and

testinstructions (SKT, SKF).

Example Set FLAG1, reset FLAG2 and test whether FLAG3 is 0 or not.

FLAG1 EQU 03FH.1 ; Address 3FH, bit 1

FLAG2 EQU 027H.2 ; Address 27H, bit 2

FLAG3 EQU 017H.0 ; Address 17H, bit 0

SET1 FLAG1 ; FLAG ← 1

CLR1 FLAG2 ; FLAG ← 0

SKF FLAG3 ; FLAG = 0?

(2) 4-bit direct addressing (mem)

An addressing mode to specify the whole data memory space directly by the instruction’s operand per 4 bits.

The specified memory bank (MB) is MB = 0 if the address specified by the operand is 00H to 3FH and MB = 15

if it is 80H to FFH. Consequently, both the static RAM area of 000H to 03FH and the peripheral hardware area of FF0H

to FFFH are addressable.

This addressing mode is applied to the MOV, XCH, INCS, IN, and OUT instructions.

Example 1. Input Port 2 and store it in “DATA1”.

DATA1 EQU 2FH ; “DATA1” is at address 2FH

IN A, PORT 2 ; A ← Port 2

MOV DATA1, A ; (DATA1) ← A

2. Output the data of “BUFF” to Port 5.

BUFF EQU 01AH ; “BUFF” is at address 01AH

MOV A, BUFF ; A ← (BUFF)

OUT PORT 5, A ; PORT 5 ← A

Contents

Main USER'S MANUAL PD75402A Page Page PREFACE USER OBJECTIVE COMPOSITION READING LEGEND Page Page Page Page CONTENTS OF FIGURES Fig. No Title Page Fig. No. Title Page Table No. Title Page CHAPTER 1. GENERAL 2 1.1 OUTLINE OF FUNCTIONS Page Page 5 1.4 BLOCK DIAGRAM PD75P402. Remarks Parentheses for the Page 7 (2) PROM mode PD75P402C/CT 8 1.5.2 44-Pin Plastic QFP ( 10mm) (1) Normal operating mode PD75P402s VPP is to be set to the GND potential. PD75P402 and the printed circuit board commonly in the Remarks Parentheses for the 9 (2) PROM mode CHAPTER 2. PIN FUNCTIONS 11 2.1 Remarks 1. In the PD75402A PIN FUNCTION LIST 2.1.1 Port Pin List Table 2-1 Port Pin List 12 2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins PD75P402 and the printed circuit board commonly, the NC pin should be connected directly to VSS. Remarks For the status of each pin at reset, see CHAPTER 8 RESET FUNCTION. *If using the Page Page Page Page Page V V Type D P.U.R. P-ch P.U.R. enable IN P-ch N-ch V Type D V OUT data output disable P-ch IN/OUT data output disable IN/OUT data output disable Page CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 22 Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode 23 Table 3-2 Addressing Mode List Page Page Page Page Page 29 Table 3-4 PD75402A I/O Map (1/2) Remarks 1. IE is an interrupt enable flag. 2. IRQ is an interrupt request flag. 30 Table 3-4 PD75402A I/O Map (2/2) CHAPTER 4. INTERNAL CPU FUNCTIONS ~ ~~ ~ Page Page Page Page Page 38 CHAPTER 4. INTERNAL CPU FUNCTIONS Fig. 4-8 Data Saved to Stack Memory Fig. 4-9 Data Restored from Stack Memory Page Page CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Page 43 Fig. 5-2 Configuration of Ports 0 and 1 Page 45 Fig. 5-4 Configuration of Ports 2 and 6 Internal Bus Output Latch Page Page Page Page 50 Table 5-3 Operations with Input/Output Port Handling Instructions Page Page Page Page Page 56 Fig. 5-11 Processor Clock Control Register Format s) as CPU clock. Note When using a calue of fXX such that 4.19 MHz < fXX 5.0 MHz, if maximum speed mode : fXX/4 (PCC1, PCC0 = 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95 Page Page Page Page Page Page Page Page Page Page () Page Page Page Page 72 Fig. 5-24 Serial Interface Block Diagram Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 109 Fig. 5-46 ACKD Operation (a) When ACK signal is output in 9th SCK clock interval Fig. 5-47 BSYE Operation (c) Clearing timing when transfer start directive is given during busy state (b) When ACK signal is output after 9th SCK clock interval HSCK SB0 111 Table 5-8 Signals in SBI Mode (2/2) 1 2 7 8 1 2 7 8 9 10 SB0 SCK Page 114 Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1) 115 Fig. 5-50 Command Transmission from Master Device to Slave Device 116 Fig. 5-51 Data Transmission from Master Device to Slave Device 117 Fig. 5-52 Data Transmission from Slave Device to Master Device Page Page Page Page Page Page Page CHAPTER 6. INTERRUPT FUNCTIONS 127 CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-1 Interrupt Control Circuit Block Diagram Page 6.3 INTERRUPT CONTROL CIRCUIT HARDWARE Page 131 CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing Page Page Page Page Page Page Page Page CHAPTER 7. STANDBY FUNCTION Page Page Page CHAPTER 8. RESET FUNCTION 147 CHAPTER 8. RESET FUNCTION Table 8-1 State of Hardware after Reset *The contents of data memory addresses 038H to 03DH are made undefined by RESET input. CHAPTER 9. INSTRUCTION SET Page Page Page Page 153 2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instructions () 154 Note Instruction Group Page Page 157 2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instruction 158 2. Branch instructions 3. I/O instructions 4. CPU control instructions MOV A, #n4 MOV rp, #n8 MOV A, @HL MOV @HL, A MOV A, mem MOV XA, mem MOV mem, A MOV mem, XA XCH A, @HL XCH A, mem XCH XA, mem XCH A, reg1 MOVT XA, @PCXA ADDS A, #n4 ADDS A, @HL ADDC A, @HL AND A, @HL Page RORC A NOT A Page Page Page Page Page BR addr BR $addr BRCB !caddr CALLF !faddr RET RETS RETI PUSH rp POP rp Page IN A, PORTn OUT PORTn, A Page 177 PD75402A and PD75402A. Since the 178 179 The following development tools are available for system development using the ~ PD75402A: Language Processor PROM Writing Tools Page 181 Development Tool Configuration