114, Chapter, Peripheral, Hardware, ACK Busy Ready

114

Master Device Processing (Transmission Side)

Program

Processing

Hardware

Operation

Transfer Line

SCK Pin

SB0 Pin

Slave Device Processing (Reception Side)

Program

Processing

Hardware

Operation

Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1)

CMDT	RELT	CMDT	Write	Interrupt Servicing
Setting	Setting	Setting	to SIO	(Preparation for Next Serial Transfer)

Serial Transmit Operation

IRQCSI

ACKD

SCK

Gene-

Stop-

ration

Setting

page

CHAPTER

PERIPHERAL

ACK

BUSY

READY

Address

HARDWARE

ACKT

BUSY

WUP

FUNCTIONS

Clear-

Setting

ance

CMDD

Serial Receive Operation

IRQCSI

ACK

BUSY

Clear-

Gene-

Output

Clear-

Setting

ance

Setting

ration

ance

	RELD		(When SVA = SIO)
	Setting		(When SVA = SIO)
	Setting

Page 125

Image 125

NEC PD75402A, PD75P402 user manual 114, Chapter, Peripheral, Hardware, ACK Busy Ready

Contents

ΜPD75402A Page Major Revisions in This Version Remarks Content to be read carefullyInstruction Functions and Application Development Tool Related Documents Related Documentation Device Related DocumentsOther Related Documents Latest documents should be used for design purposes, etc Contents Interrupt Control Circuit Configuration Basic Interval TimerDigital INPUT/OUTPUT Ports Clock Generation Circuit Standby Mode Reset Standby Mode Setting and Operation StatesOperation After Standby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Table No Title Contents of Tables ECR VCR GeneralFAX PPC For details, see Interrupt Functions General Outline of Functions Quality Grade General Ordering Information and Quality GradeOrdering Information VPP PORT0 PORT1 PORT2 PORT3 PORT5 Block DiagramINT0 Interrupt INT2 Control PORT6 SCK General PIN ConfigurationSO/SB0 VPP NC Prom mode NC NC NC P50 2 44-Pin Plastic QFP 10mm Normal operating modeP01/SCK NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions SCK ΜPD75402A PIN Function List Port Pin ListSO/SB0 INT0 SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode PCL ..... Port 2 Dual-Function Output 4 INT0 ..... Port 1 Dual-Function Input5 INT2 ..... Port 1 Dual-Function Input 7 X1, X2 Crystal Reset Reset CE Chip Enable ..... Input PIN Functions Prom ModeOE Output Enable ..... Input 1 A0 to A14 Address ..... Input Pin Input/output Types PIN Functions PIN INPUT/OUTPUT CircuitsRemarks a circle P22/PCL IN/OUT OUT Type F B Type M a PIN Functions Unused PIN Treatment P00, Reset Data Memory Bank Configuration Features of Architecture and Memory MAP FF0H Fffh FB0HFbfh @HL Addressing Mode List Bit direct addressing mem Data Memory Addressing ModesBit direct addressing mem.bit Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit SUB Push POP RET Stack addressingPush HL POP Push HL Push XA RET Applicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/O ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 PC1 PC0 Internal CPU FunctionsProgram Counter PC .... Bits Program Memory Map Program Memory ROM .... ,920 Words × 8 Bits Data area Internal CPU Functions Data Memory RAMGeneral register area Stack area Peripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register Configuration Accumulators Internal CPU Functions Accumulator Range of 020H to 03FH Internal CPU Functions Stack Pointer SP .... BitsMOV SP, XA SP4 SP3 SP2 SP1 SP0 IST0 PSW Data Saved to Stack Memory Carry Flag Manipulation Instructions Internal CPU Functions Program Status Word PSW .... BitsCarry flag CY SET1 Interrupt Status Flag Indication ContentSkip flag SK2, SK1, SK0 Interrupt status flag IST0 PORT0 Peripheral Hardware Functions Digital Input/Output Port Types and Characteristics PO0 Csim PogaPO1 INT2 INT0 PO3 Configuration of Port Configuration of Ports 2 PM5 Pmgb Input/Output Mode Setting Fech PM5 PM2 Pmgb Digital Input/Output Port Handling InstructionsPmga Bit handling instructions Digital Input/Output Port Operations Operations when input mode is setOperations when output mode is set Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each Port Fdch PO6 PO3 PO2 PO1 PO0 MOV POGA, XAPORT1 Data fetch by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instruction Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Configuration Processor clock control register PCC Clock Generation Circuit Function and OperaionSEL MOV PCC, a PCC FB3H PCC3 PCC2 PCC1 PCC0 12 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit 13 Example of Poor Resonator Connection Circuit 2/2 Example CPU Clock SettingUse of Variable Minimum Instruction Execution Time Function Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On Reset Differences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register Format P22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Circuit ConfigurationPeripheral Hardware Functions Clock Output Circuit Clom Clock Output Mode Register Clom Examle of Remote Control Application Clock Output Procedure Basic Interval Timer Configuration Peripheral Hardware Functions Basic Interval TimerMPX BTM3 BTM2 MOV BTM. a Basic Intercal Timer Mode Register BTMBTM3 BTM From the beginning Basic Interval Timer Operation MOV BTM,A Examples of Basic Interval Timer ApplicationsIebt SEL MOV Wire serial I/O mode Operation-halted modePeripheral Hardware Functions Serial Interface Serial Interface Functions Serial Interface Configuration SBI mode serial bus interface mode Functions Serial Interface Block Diagram Serial bus interface control register Sbic Serial operating mode register CsimShift register SIO SO latch Serial clock control circuit Register Functions Serial operating mode register CsimIntcsi control circuit Csie COI WUP CSIM3 CSIM1 Csim Serial interface operating mode selection bit WSerial clock selection bit W Csie Signal from address comparator R SET1 Csie MOV CSIM, XACsie CSIM3 Csie CSIM1 Cmdd Reld Cmdt Relt FE2H Command detection flag R Command trigger bit WBus release detection flag R Acknowledge trigger bit W Acknowledge detection flag R Busy enable bit R/W BUSY/ACK SIOCLK See 5.5.6 8 Error detection for details Error detectionSlave address register SVA Slave address detection Csie C0I WUP CSIM3 CSIM1 Csim Register setting 28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode Operation Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bit Communication operation 29 3-Wire Serial I/O Mode Timing Signals Serial Clock Selection and Use in 3-Wire Serial I/O ModeSerial clock selection Relt Cmdt Start of transfer Data transfer order MOV XA, Tdata Wire serial I/O mode applicationsMOV SIO, XA SCK SO/SB0 Iecsi MOV XA, Tdata SIO, XAMOV XA, Tdata XCH XA, SIO MOV RDATA, XA + VDD SBI Mode OperationCPU SB0 SCK SB0 SCK Acknowledge signal ACK control function Address/command/data differentiation functionBusy signal Busy control function SBI functions SB0 ACK SBI definitionSB0 C0 ACK Busy SB0 D0 ACK Busy Command signal CMD Bus release signal RELSCK H SCK H SB0 37 Slave Selection by Address Address Data Command & data SCK SB0 ACK Acknowledge signal ACK SCK SB0 ACK Busy Busy signal BUSY, ready signal Ready100 101 102 103 104 105 Serial Clock Selection and Use in SBI Mode 106 RELT, CMDT, Reld & Cmdd Operation SlaveSIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK 107 44 Ackt Operation When Acke = 0 on completion of transfer When Acke is set after completion of transferWhen Acke = 1 interval is short 108 109 When ACK signal is output after 9th SCK clock intervalSCK SB0 ACK Ackd SCK SB0 Bsye ACK SCK Cmdd 110 Signals in SBI ModeSB0 ACK Ready SB0 Ready REL CMD 111 Pin Configuration Diagram Pin configuration 113 Address match detection methodUse of slave address register SVA Chapter 114Peripheral Hardware 115 50 Command Transmission from Master Device to Slave 51 Data Transmission from Master Device to Slave Device 116 117 52 Data Transmission from Slave Device to Master Device 118 Points to note concerning SBI mode 119 SBI mode applicationSerial bus configuration 120 Description of commands Command typesIi Communication procedure ➀ Read command Iii Command formats➁ WRITE, END and Stop commands 121 ACK Stop 122MSM 123 ➂ Status commandStatus MSB LSB ➄ Chgmst command Reset command124 Chgmst Errors generated on the slave side Iv Error occurrenceErrors generated on the master side 125 Interrupt Functions 127 Interrupt Request Source Types Interrupt Functions Interrupt Source Types and Vector TableVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0 Interrupt Request Flag Setting Signal Interrupt request flag & interrupt enable flagExample EI IE0 130 External interrupt input pin hardware INT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output Timing 132 Interrupt master enable flag IMEFB4H IM03 FB2H 133 Interrupt status flagIST0 Interrupt Servicing Status IME=1 Interrupt Functions Interrupt SequenceYES Interrupt INTxxx generation 136 EI Iecsi Interrupt Functions Interrupt ApplicationsInterrupt enabling/disabling 138 Example using INTBT, INT0 falling edge active, and IntcsiCLR1 IRQ0 ➄ Reti EI IE0 139➂ Intcsi Reti ➃ EI Iecsi Reti INT0 Intcsi ➁ Reti Pending interrupt execution140 Standby Function Stop modeHalt mode Standby Mode Operation States Standby Function Standby Mode Setting and Operation States Stop mode reset by Reset input Standby Function Standby Mode ResetHalt mode reset by Reset input Halt mode reset by interrupt generation Halt 144 IME = Standby Function Operation After Standby Mode Reset Reset at Power-on Reset Signal Acceptance OFF State of Hardware after Reset147 148 Architecture and Memory MAP Bit Manipulation Instructions Instruction SET Special InstructionsStack Instructions Example A0 Base correction at addition Base Correction InstructionsAddc Adds Addc Operation description legend Instruction SET Instruction SET and ITS OperationOperation identifier and description 152 Description of addressing area field symbolsDescription of machine cycle field Adds Movt XA, @PCXAAddc XOR 154 Instructions Instruction Group155 NOP Instruction SET Operation Code of Each Instruction Description of operation code symbolsBit manipulation addressing operation code Iebt Iecsi IE0 IE2 SET CLR SKT Not Rorc Not Incs Halt Stop NOP RET Rets Reti Push POP Move Instructions Instruction SET Instruction Functions and ApplicationMOV A, #0BH MOV HL, #5FH 160 MOV XA, 20H 161 Loop XCHMOV XCH Table data on that Table Reference Instructions162 02FFH 163 Arithmetic and Logic InstructionsSee section 164 Or A, @HL 165 Rorc a 166 Incs reg 167 SKE reg, #n4 168 Carry Flag Operation Instructions 169 Bit Manipuration Instructions 170 SKF mem. bit 171 BR addr 172 Subroutine Stack Control Instructions 173 Push rp 174 Interrupt Control Instructions 175 Input/Output Instructions 176 Halt 177 178 179 Language ProcessorProm Writing Tools 180 Debugging Tools IBM PC/AT Development Tool Configuration181 182 183 Irqcs 184Pmgb Cmdd Port