NEC PD75P402 Command trigger bit W, Bus release detection flag R, Command detection flag R

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3)

Bus release trigger bit (W)

RELT

The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this bit (RELT = 1), after which the RELT bit is automatically cleared (0).

Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after it is completed.

Command trigger bit (W)

CMDT

The command signal (CMD) trigger output control bit. The SO latch is cleared (0) by setting this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).

Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after it is completed.

Bus release detection flag (R)

RELD

Clearing Conditions (RELD = 0) Setting Condition (RELD = 1)

➀When a transfer start instruction is executed

➁	When RESET is input	When the bus release signal (REL) is de-
➂	When CSIE = 0 (See Fig. 5-25)
		tected

4When SVA and SIO do not match when an address is received

Command detection flag (R)

CMDD

Clearing Conditions (CMDD = 0) Setting Condition (CMDD = 1)

➀When a transfer start instruction is executed

➁	When tje bus release signal (REL) is	When the command signal (CMD) is de-
	detected
		tected
➂	When RESET is input

4When CSIE = 0 (See Fig. 5-25)

Acknowledge trigger bit (W)

ACKT

When ACKT is set after the end of a transfer, ACK is output in synchronization with the next SCK. After th ACK signal is output, ACKT is automatically cleared (0).

Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a transfer.

2.ACKT cannot be clearedby software.

3.When ACKT is set, ACKE should be reset to 0.

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