Main
USER'S MANUAL
PD75402A
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PREFACE USER
OBJECTIVE
COMPOSITION
READING
LEGEND
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CONTENTS OF FIGURES Fig. No Title Page
Fig. No. Title Page
Table No. Title Page
CHAPTER 1. GENERAL
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1.1 OUTLINE OF FUNCTIONS
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1.4 BLOCK DIAGRAM
PD75P402.
Remarks Parentheses for the
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(2) PROM mode
PD75P402C/CT
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1.5.2 44-Pin Plastic QFP ( 10mm) (1) Normal operating mode
PD75P402s VPP is to be set to the GND potential.
PD75P402 and the printed circuit board commonly in the
Remarks Parentheses for the
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(2) PROM mode
CHAPTER 2. PIN FUNCTIONS
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2.1
Remarks 1. In the
PD75402A PIN FUNCTION LIST 2.1.1 Port Pin List Table 2-1 Port Pin List
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2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins
PD75P402 and the printed circuit board commonly, the NC pin should be connected directly to VSS.
Remarks For the status of each pin at reset, see CHAPTER 8 RESET FUNCTION. *If using the
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V
V
Type D
P.U.R.
P-ch P.U.R. enable IN
P-ch N-ch
V
Type D
V
OUT
data output disable
P-ch IN/OUT
data output disable
IN/OUT
data output disable
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
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Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode
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Table 3-2 Addressing Mode List
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Table 3-4
PD75402A I/O Map (1/2)
Remarks 1. IE is an interrupt enable flag. 2. IRQ is an interrupt request flag.
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Table 3-4
PD75402A I/O Map (2/2)
CHAPTER 4. INTERNAL CPU FUNCTIONS
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CHAPTER 4. INTERNAL CPU FUNCTIONS Fig. 4-8 Data Saved to Stack Memory
Fig. 4-9 Data Restored from Stack Memory
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
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Fig. 5-2 Configuration of Ports 0 and 1
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Fig. 5-4 Configuration of Ports 2 and 6
Internal Bus Output Latch
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Table 5-3 Operations with Input/Output Port Handling Instructions
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Fig. 5-11 Processor Clock Control Register Format
s) as CPU clock.
Note When using a calue of fXX such that 4.19 MHz < fXX 5.0 MHz, if maximum speed mode :
fXX/4 (PCC1, PCC0 = 11) is set as CPU clock frequency, 1 machine cycle is less than 0.95
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Fig. 5-24 Serial Interface Block Diagram
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Fig. 5-46 ACKD Operation (a) When ACK signal is output in 9th SCK clock interval
Fig. 5-47 BSYE Operation
(c) Clearing timing when transfer start directive is given during busy state
(b) When ACK signal is output after 9th SCK clock interval
HSCK SB0
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Table 5-8 Signals in SBI Mode (2/2)
1 2 7 8
1 2 7 8 9 10 SB0
SCK
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Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1)
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Fig. 5-50 Command Transmission from Master Device to Slave Device
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Fig. 5-51 Data Transmission from Master Device to Slave Device
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Fig. 5-52 Data Transmission from Slave Device to Master Device
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CHAPTER 6. INTERRUPT FUNCTIONS
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CHAPTER 6. INTERRUPT FUNCTIONS
Fig. 6-1 Interrupt Control Circuit Block Diagram
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6.3 INTERRUPT CONTROL CIRCUIT HARDWARE
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CHAPTER 6. INTERRUPT FUNCTIONS Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing
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CHAPTER 7. STANDBY FUNCTION
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CHAPTER 8. RESET FUNCTION
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CHAPTER 8. RESET FUNCTION Table 8-1 State of Hardware after Reset
*The contents of data memory addresses 038H to 03DH are made undefined by RESET input.
CHAPTER 9. INSTRUCTION SET
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2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instructions
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Note Instruction Group
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2. Accumulator operation instructions 3. Increment/decrement instructions 4. Compare instruction
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2. Branch instructions 3. I/O instructions 4. CPU control instructions
MOV A, #n4
MOV rp, #n8
MOV A, @HL
MOV @HL, A
MOV A, mem
MOV XA, mem
MOV mem, A
MOV mem, XA
XCH A, @HL
XCH A, mem
XCH XA, mem
XCH A, reg1
MOVT XA, @PCXA
ADDS A, #n4
ADDS A, @HL
ADDC A, @HL
AND A, @HL
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RORC A
NOT A
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BR addr
BR $addr
BRCB !caddr
CALLF !faddr
RET
RETS
RETI
PUSH rp
POP rp
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IN A, PORTn
OUT PORTn, A
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PD75402A and
PD75402A. Since the
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The following development tools are available for system development using the
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PD75402A: Language Processor
PROM Writing Tools
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Development Tool Configuration
38CHAPTER 4. INTERNAL CPU FUNCTIONSFig. 4-8 Data Saved to Stack Memory