NEC PD75P402 INT0 Noise Elimination Circuit Input/Output Timing, INT2 Input Noise Elimination

CHAPTER 6. INTERRUPT FUNCTIONS

Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing

		tSMP	tSMP	tSMP	tSMP		tSMP
➀ Sampling Cycle		L		L
(tSMP) or Less
	INT0
	Sheped		Eliminated as Noise
	Output
➁ 1 to 2 Times tSMP		H		H
					L	L
(a)	INT0
	Sheped
	Output
				H
		L			L	L
(b)	INT0
	Sheped		Eliminated as Noise
	Output
➂ 2 or More Times		H		H		L	L
tSMP
	INT0
	Sheped
	Output

Remarks tSMP = tCY or 64/fXX

Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge detection mode register (IM0).

As signals are also input via the noise elimination circuit when the INT0 pin inputs data as a port, the input data must be of sufficient width to avoid being eliminated as noise.

INT2 functions as an externally testable input which sets a testable flag on detection of a rising edge. Noise elimination by the sampling clock is not performed, but as there is a function for eliminating pulses which are narrower than the analog delay, a signal of adequate width must be input as in the case of INT0 (see Fig. 6-5).

Fig. 6-5 INT2 Input Noise Elimination

INT2 Input

Analog	Analog
Delay	Delay
Eliminated	INT2 Input
as Noise	Received

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