NEC PD75402A, PD75P402 user manual Standby Function Standby Mode Setting and Operation States

CHAPTER 7. STANDBY FUNCTION

7.1STANDBY MODE SETTING AND OPERATION STATES

Table 7-1 Standby Mode Operation States

			STOP Mode		HALT Mode
	Setting instruction	STOP instruction			HALT instruction
	Clock generator	Clock oscillation stopped			CPU clock Φ only stopped oscillator
					(oscillation continues)
	Basic interval timer	Operation stopped			Operation
state					(IRQBT set at basic time interval)
	Serial interface	Operation possible only when external			Operation possible
Operation
		SCK input selected as serial clock
	Clock output circuit	Operation stopped			Output other than CPU clock Φ possible
	External interrupt		INT2	: Operation possible
			INT0	: Operation impossible
	CPU			Operation stopped
					Interrupt request signal from operable
	Reset signal	RESET input
					hardware enabled by interrupt enable
					flag or RESET input.

The STOP mode is set by STOP instruction and the HALT mode is set by HALT instruction. (The STOP instruction and HALT instruction set bits 3 and 2 of the PCC respectively.)

Always write an NOP instruction after the STOP instruction or HALT instruction.

When the CPU operation clock is changed by means of the low-order two bits of the PCC, a time lag may be generated between rewriting of the PCC and changing of the CPU clock. Therefore, when changing the operating clock before the standby mode and when changing the CPU clock after standby mode reset, set the standby mode after the number of machine cycles required to change the CPU clock has elapsed after the PCC is rewritten.

In the standby mode, the data of the general register, flags, mode registers, output latch, and all the other registers which stop operating in the standby mode and the data memory is retained.

Notes are given below.

Note 1. When the STOP mode is set, the X1 pin is shorted internally to VSS (GND potential) to suppress clock oscillator leakage. Therefore, do not use the STOP mode with systems that use an external clock.

2.STOP mode reset by interrupt request differs as follows for the μPD75402A and the evachip installed on the evaluation board:

•μPD75402A•••••• STOP mode not reset by interrupt request.

•Evachip •••••••••••••• STOP mode reset by interrupt request.

To eliminate the affect of this difference, disable all interrupt requests before setting the μPD75402A to the STOP mode.

3.From the standpoint that an interrupt request signal is used to reset the HALT mode, when there is an interrupt source which sets both the interrupt request flag and interrupt enable flag (1), the HALT mode, even if entered, is immediately reset.

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