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CHAPTER 9. INSTRUCTION SET
mem. bit 2 2 (mem. bit) ← 1*2
f mem. bit 2 2 (f mem.bit) ← 1*3
mem. bit 2 2 (mem. bit) ← 0*2
f mem. bit 2 2 (f mem. bit) ← 0*3
mem. bit 2 2 + S Skip if (mem. bit) = 1 *2 (mem. bit) = 1
f mem. bit 2 2 + S Skip if (f mem. bit) = 1 *3 (f mem. bit) = 1
mem. bit 2 2 + S Skip if (mem. bit) = 0 *2 (mem. bit) = 0
f mem. bit 2 2 + S Skip if (f mem. bit) = 0 *3 (f mem. bit) = 0
SKTCLR f mem. bit 2 2 + S Skip if (f mem. bit) = 1 and clear *3 (f mem. bit) = 1
AND 1 CY, f mem. bit 2 2 CY ← CY ∧ (f mem. bit) *3
OR 1 CY, f mem. bit 2 2 CY ← CY ∨ (f mem. bit) *3
XOR 1 CY, f mem. bit 2 2 CY ← CY ∨ (f mem. bit) *3
addr – – PC 10 – 0 ← addr *4
BR
$addr 1 2 PC 10 – 0 ← addr *5
BRCB ! caddr 2 2 PC 10 – 0 ← caddr *6
(SP–4) (SP –1) (SP–2) ← 0, PC 10 – 0
CALLF ! faddr 2 2 (SP – 3) ← 0000 *7
PC 10 – 0 ← faddr, SP ← SP – 4
PC 10 – 0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
PC 10 – 0 (SP) (SP + 3) (SP + 2)
RETS 1 3 + S SP ← SP + 4, None
then skip unconditionally
PC 10 – 0 ← (SP) (SP + 3) (SP + 2)
RETI 1 3 PSW ← (SP + 4) (SP + 5),
SP ← SP + 6
PUSH rp 1 1 (SP–1) (SP–2) ← rp, SP ← SP–2
POP rp 1 1 rp ← (SP + 1) (SP) , SP ← SP + 2
2 2 IME (IPS. 3) ← 1
IE××× 22IE××× ← 1
2 2 IME (IPS. 3) ← 0
IE××× 22IE××× ← 0
Skip
Condition
Addressing
Area
Mnemonic Operand Operation
CLR 1
SKT
SKF
SET 1
Note Bytes Machine
Cycle
The assembler selects the opti-
mum instruction from among
BRCB!, caddr, and BR$ addr.
RET 1 3
DI
EI
Branch
instructions
Subroutine stack control instructions
Interrupt control
instructions
Bit manipulation instructions