Peripheral hardware area, Mov | NEC PD75402A, PD75P402 manual

CHAPTER 4. INTERNAL CPU FUNCTIONS

(2) Peripheral hardware area

The peripheral hardware area is mapped to memory bank 15’s addresses F80H to FFFH.

The operation is performed by the memory manipulation instruction just as in the static RAM. In the peripheral hardware, however, the operable bit unit differs from one address to another. It is impossible to access an address to which the peripheral hardware is not assigned since the data memory is not built in. (See Table 3-4 “μPD75402A I/O Map".)

Note The static RAM is indefinite at reset. Therefore, it should be initialized to zero at the beginning of the

program (RAM clear). This must be carried out for sure to avoid unexpected bugs.

Example Clear all the areas (00H to 3FH) of the static RAM (FFH remains in the HL register, however).

	MOV	HL, #3FH
	MOV	A, #0H
LOOP:	MOV	@HL, A: Clear (0) 00H to 3FH
	DECS	L
	BR	LOOP
	DECS	H
	BR	LOOP

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NEC PD75402A, PD75P402 user manual Peripheral hardware area, Mov

Contents

ΜPD75402A Page Major Revisions in This Version Content to be read carefully Instruction Functions and ApplicationRemarks Development Tool Related Documents Related Documentation Device Related DocumentsOther Related Documents Latest documents should be used for design purposes, etc Contents Interrupt Control Circuit Configuration Basic Interval TimerDigital INPUT/OUTPUT Ports Clock Generation Circuit Standby Mode Reset Standby Mode Setting and Operation StatesOperation After Standby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Table No Title Contents of Tables General FAX PPCECR VCR For details, see Interrupt Functions General Outline of Functions General Ordering Information and Quality Grade Ordering InformationQuality Grade VPP PORT0 PORT1 PORT2 PORT3 PORT5 Block DiagramINT0 Interrupt INT2 Control PORT6 SCK General PIN ConfigurationSO/SB0 VPP NC Prom mode NC NC NC P50 2 44-Pin Plastic QFP 10mm Normal operating modeP01/SCK NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions SCK ΜPD75402A PIN Function List Port Pin ListSO/SB0 INT0 SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode 4 INT0 ..... Port 1 Dual-Function Input 5 INT2 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output 7 X1, X2 Crystal Reset Reset CE Chip Enable ..... Input PIN Functions Prom ModeOE Output Enable ..... Input 1 A0 to A14 Address ..... Input Pin Input/output Types PIN Functions PIN INPUT/OUTPUT CircuitsRemarks a circle P22/PCL IN/OUT OUT Type F B Type M a PIN Functions Unused PIN Treatment P00, Reset Data Memory Bank Configuration Features of Architecture and Memory MAP FB0H FbfhFF0H Fffh @HL Addressing Mode List Data Memory Addressing Modes Bit direct addressing mem.bitBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit SUB Push POP RET Stack addressingPush HL POP Push HL Push XA RET Applicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/O ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Internal CPU Functions Program Counter PC .... BitsPC1 PC0 Program Memory Map Program Memory ROM .... ,920 Words × 8 Bits Data area Internal CPU Functions Data Memory RAMGeneral register area Stack area Peripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register Configuration Accumulators Internal CPU Functions Accumulator Range of 020H to 03FH Internal CPU Functions Stack Pointer SP .... BitsMOV SP, XA SP4 SP3 SP2 SP1 SP0 IST0 PSW Data Saved to Stack Memory Internal CPU Functions Program Status Word PSW .... Bits Carry flag CYCarry Flag Manipulation Instructions SET1 Interrupt Status Flag Indication ContentSkip flag SK2, SK1, SK0 Interrupt status flag IST0 PORT0 Peripheral Hardware Functions Digital Input/Output Port Types and Characteristics PO0 Csim PogaPO1 INT2 INT0 PO3 Configuration of Port Configuration of Ports 2 PM5 Pmgb Input/Output Mode Setting Digital Input/Output Port Handling Instructions PmgaFech PM5 PM2 Pmgb Bit handling instructions Operations when input mode is set Operations when output mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each Port MOV POGA, XA PORT1Fdch PO6 PO3 PO2 PO1 PO0 Data fetch by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instruction Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Configuration Processor clock control register PCC Clock Generation Circuit Function and OperaionSEL MOV PCC, a PCC FB3H PCC3 PCC2 PCC1 PCC0 12 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit 13 Example of Poor Resonator Connection Circuit 2/2 CPU Clock Setting Use of Variable Minimum Instruction Execution Time FunctionExample Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On Reset Differences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register Format Clock Output Circuit Configuration Peripheral Hardware Functions Clock Output CircuitP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clom Clock Output Mode Register Clom Examle of Remote Control Application Clock Output Procedure Basic Interval Timer Configuration Peripheral Hardware Functions Basic Interval TimerMPX BTM3 BTM2 MOV BTM. a Basic Intercal Timer Mode Register BTMBTM3 BTM From the beginning Basic Interval Timer Operation MOV BTM,A Examples of Basic Interval Timer ApplicationsIebt SEL MOV Wire serial I/O mode Operation-halted modePeripheral Hardware Functions Serial Interface Serial Interface Functions Serial Interface Configuration SBI mode serial bus interface mode Functions Serial Interface Block Diagram Serial bus interface control register Sbic Serial operating mode register CsimShift register SIO SO latch Register Functions Serial operating mode register Csim Intcsi control circuitSerial clock control circuit Serial interface operating mode selection bit W Serial clock selection bit WCsie COI WUP CSIM3 CSIM1 Csim Csie Signal from address comparator R SET1 Csie MOV CSIM, XACsie CSIM3 Csie CSIM1 Cmdd Reld Cmdt Relt FE2H Command detection flag R Command trigger bit WBus release detection flag R Acknowledge trigger bit W Acknowledge detection flag R Busy enable bit R/W SIO CLKBUSY/ACK See 5.5.6 8 Error detection for details Error detectionSlave address register SVA Slave address detection Csie C0I WUP CSIM3 CSIM1 Csim Register setting 28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode Operation Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bit Communication operation 29 3-Wire Serial I/O Mode Timing Signals Serial Clock Selection and Use in 3-Wire Serial I/O ModeSerial clock selection Relt Cmdt Start of transfer Data transfer order MOV XA, Tdata Wire serial I/O mode applicationsMOV SIO, XA SCK SO/SB0 Iecsi MOV XA, Tdata SIO, XAMOV XA, Tdata XCH XA, SIO MOV RDATA, XA + VDD SBI Mode OperationCPU SB0 SCK SB0 SCK Acknowledge signal ACK control function Address/command/data differentiation functionBusy signal Busy control function SBI functions SB0 ACK SBI definitionSB0 C0 ACK Busy SB0 D0 ACK Busy Command signal CMD Bus release signal RELSCK H SCK H SB0 37 Slave Selection by Address Address Data Command & data SCK SB0 ACK Acknowledge signal ACK Busy signal BUSY, ready signal Ready 100SCK SB0 ACK Busy 101 102 103 104 105 Serial Clock Selection and Use in SBI Mode 106 RELT, CMDT, Reld & Cmdd Operation SlaveSIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK 107 44 Ackt Operation When Acke = 0 on completion of transfer When Acke is set after completion of transferWhen Acke = 1 interval is short 108 109 When ACK signal is output after 9th SCK clock intervalSCK SB0 ACK Ackd SCK SB0 Bsye ACK SCK Cmdd 110 Signals in SBI ModeSB0 ACK Ready SB0 Ready REL CMD 111 Pin Configuration Diagram Pin configuration Address match detection method Use of slave address register SVA113 Chapter 114Peripheral Hardware 115 50 Command Transmission from Master Device to Slave 51 Data Transmission from Master Device to Slave Device 116 117 52 Data Transmission from Slave Device to Master Device 118 Points to note concerning SBI mode SBI mode application Serial bus configuration119 Description of commands Command types Ii Communication procedure120 ➀ Read command Iii Command formats➁ WRITE, END and Stop commands 121 122 MSMACK Stop 123 ➂ Status commandStatus MSB LSB ➄ Chgmst command Reset command124 Chgmst Errors generated on the slave side Iv Error occurrenceErrors generated on the master side 125 Interrupt Functions 127 Interrupt Request Source Types Interrupt Functions Interrupt Source Types and Vector TableVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0 Interrupt Request Flag Setting Signal Interrupt request flag & interrupt enable flagExample EI IE0 130 External interrupt input pin hardware INT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output Timing 132 Interrupt master enable flag IMEFB4H IM03 FB2H Interrupt status flag IST0 Interrupt Servicing Status133 Interrupt Functions Interrupt Sequence YESIME=1 Interrupt INTxxx generation 136 Interrupt Functions Interrupt Applications Interrupt enabling/disablingEI Iecsi 138 Example using INTBT, INT0 falling edge active, and IntcsiCLR1 IRQ0 ➄ Reti EI IE0 139➂ Intcsi Reti ➃ EI Iecsi Reti Pending interrupt execution 140INT0 Intcsi ➁ Reti Stop mode Halt modeStandby Function Standby Mode Operation States Standby Function Standby Mode Setting and Operation States Stop mode reset by Reset input Standby Function Standby Mode ResetHalt mode reset by Reset input Halt mode reset by interrupt generation Halt 144 IME = Standby Function Operation After Standby Mode Reset Reset at Power-on Reset Signal Acceptance State of Hardware after Reset 147OFF 148 Architecture and Memory MAP Bit Manipulation Instructions Instruction SET Special InstructionsStack Instructions Example A0 Base correction at addition Base Correction InstructionsAddc Adds Addc Instruction SET Instruction SET and ITS Operation Operation identifier and descriptionOperation description legend Description of addressing area field symbols Description of machine cycle field152 Adds Movt XA, @PCXAAddc XOR 154 Instructions Instruction Group155 NOP Instruction SET Operation Code of Each Instruction Description of operation code symbolsBit manipulation addressing operation code Iebt Iecsi IE0 IE2 SET CLR SKT Not Rorc Not Incs Halt Stop NOP RET Rets Reti Push POP Move Instructions Instruction SET Instruction Functions and ApplicationMOV A, #0BH MOV HL, #5FH 160 MOV XA, 20H Loop XCH MOV XCH161 Table data on that Table Reference Instructions162 02FFH Arithmetic and Logic Instructions See section163 164 Or A, @HL 165 Rorc a 166 Incs reg 167 SKE reg, #n4 168 Carry Flag Operation Instructions 169 Bit Manipuration Instructions 170 SKF mem. bit 171 BR addr 172 Subroutine Stack Control Instructions 173 Push rp 174 Interrupt Control Instructions 175 Input/Output Instructions 176 Halt 177 178 Language Processor Prom Writing Tools179 180 Debugging Tools Development Tool Configuration 181IBM PC/AT 182 183 Irqcs 184Pmgb Cmdd Port

CHAPTER 4. INTERNAL CPU FUNCTIONS

(2) Peripheral hardware area

MOV

DECS