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NEC PD75P402, PD75402A Stack addressing, SUB Push POP RET, Push HL POP, Push HL Push XA RET

Models: PD75402A PD75P402

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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

(6) Stack addressing

This addressing mode is for the saving/restoring operation during the interrupting process, subroutine process. The data memory is addressed indirectly according to the content of the stack pointer (SP : 8 bits).

The memory bank (MB) addressed in this addressing mode is fixed to 0. Also as the stack pointer’s high-order 3 bits are fixed to 001, the addressable area is limited to 020H to 03FH.

This addressing mode is also applied at register save/restore by the PUSH, POP instruction in addition to the interrupting process, subroutine process.

Note The Evachip packaged on the board for evaluation can address the whole area of Memory bank 0 in this addressing mode unlike in the μPD75402A. To eliminate such a difference during the evaluation, a value

not to access beyond the range of 20H to 3FH should be set in the stack pointer.

Example 1. Save/restore the register during the subroutine process.

SUB:	PUSH	XA
	PUSH	HL
		........
	POP	HL
	POP	XA
	RET

2.Transfer the content of the HL register pair to the XA register pair.

PUSH HL

POP

XA

; XA ← HL

3.Branch to the address indicated by the (XAHL) register.

PUSH HL

PUSH XA

RET	; Branch to address XAHL

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NEC PD75P402, PD75402A user manual Stack addressing, SUB Push POP RET, Push HL POP, Push HL Push XA RET

Contents

ΜPD75402A Page Major Revisions in This Version Remarks Content to be read carefullyInstruction Functions and Application Other Related Documents Related Documentation Device Related DocumentsDevelopment Tool Related Documents Latest documents should be used for design purposes, etcContents Digital INPUT/OUTPUT Ports Basic Interval TimerInterrupt Control Circuit Configuration Clock Generation CircuitOperation After Standby Mode Reset Standby Mode Setting and Operation StatesStandby Mode Reset Standby Mode ApplicationContents of Figures Fig. No Title Contents of Tables Table No TitleECR VCR GeneralFAX PPC General Outline of Functions For details, see Interrupt FunctionsQuality Grade General Ordering Information and Quality GradeOrdering Information VPP INT0 Interrupt INT2 Control Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 PORT6SO/SB0 General PIN ConfigurationSCK VPP NCProm mode P01/SCK 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 NC V SS NC P22/PCLA2 NC NC NC NC PIN Functions SO/SB0 ΜPD75402A PIN Function List Port Pin ListSCK INT0SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function PinsPCL ..... Port 2 Dual-Function Output 4 INT0 ..... Port 1 Dual-Function Input5 INT2 ..... Port 1 Dual-Function Input Reset Reset 7 X1, X2 CrystalOE Output Enable ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input 1 A0 to A14 Address ..... InputRemarks a circle PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types P22/PCLOUT IN/OUTType F B Type M a P00, Reset PIN Functions Unused PIN TreatmentFeatures of Architecture and Memory MAP Data Memory Bank ConfigurationFF0H Fffh FB0HFbfh Addressing Mode List @HLBit direct addressing mem Data Memory Addressing ModesBit direct addressing mem.bit Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL POP Stack addressingSUB Push POP RET Push HL Push XA RETFeatures of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware OperationΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 PC1 PC0 Internal CPU FunctionsProgram Counter PC .... Bits Program Memory ROM .... ,920 Words × 8 Bits Program Memory MapGeneral register area Internal CPU Functions Data Memory RAMData area Stack areaPeripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 BitsInternal CPU Functions Accumulator AccumulatorsMOV SP, XA Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH SP4 SP3 SP2 SP1 SP0Data Saved to Stack Memory IST0 PSWCarry Flag Manipulation Instructions Internal CPU Functions Program Status Word PSW .... BitsCarry flag CY Skip flag SK2, SK1, SK0 Interrupt Status Flag Indication ContentSET1 Interrupt status flag IST0Peripheral Hardware Functions PORT0Digital Input/Output Port Types and Characteristics PO1 Csim PogaPO0 INT2 INT0Configuration of Port PO3Configuration of Ports 2 Input/Output Mode Setting PM5 PmgbFech PM5 PM2 Pmgb Digital Input/Output Port Handling InstructionsPmga Bit handling instructions Digital Input/Output Port Operations Operations when input mode is setOperations when output mode is set Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up ResistorsFdch PO6 PO3 PO2 PO1 PO0 MOV POGA, XAPORT1 Data latching by 1-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 2-machine-cycle instructionClock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation CircuitSEL Clock Generation Circuit Function and OperaionProcessor clock control register PCC MOV PCC, aFB3H PCC3 PCC2 PCC1 PCC0 PCCSystem clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry13 Example of Poor Resonator Connection Circuit 2/2 Example CPU Clock SettingUse of Variable Minimum Instruction Execution Time Function 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU ClockDifferences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1P22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Circuit ConfigurationPeripheral Hardware Functions Clock Output Circuit Clock Output Mode Register Clom ClomClock Output Procedure Examle of Remote Control ApplicationMPX Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration BTM3 BTM2BTM3 Basic Intercal Timer Mode Register BTMMOV BTM. a BTMBasic Interval Timer Operation From the beginningIebt Examples of Basic Interval Timer ApplicationsMOV BTM,A SEL MOVPeripheral Hardware Functions Serial Interface Operation-halted modeWire serial I/O mode Serial Interface FunctionsSBI mode serial bus interface mode Serial Interface ConfigurationSerial Interface Block Diagram FunctionsShift register SIO Serial operating mode register CsimSerial bus interface control register Sbic SO latchSerial clock control circuit Register Functions Serial operating mode register CsimIntcsi control circuit Csie COI WUP CSIM3 CSIM1 Csim Serial interface operating mode selection bit WSerial clock selection bit W Signal from address comparator R CsieCsie CSIM3 MOV CSIM, XASET1 Csie Csie CSIM1FE2H Cmdd Reld Cmdt ReltBus release detection flag R Command trigger bit WCommand detection flag R Acknowledge trigger bit WBusy enable bit R/W Acknowledge detection flag RBUSY/ACK SIOCLK Slave address register SVA Error detectionSee 5.5.6 8 Error detection for details Slave address detectionRegister setting Csie C0I WUP CSIM3 CSIM1 Csim5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System ConfigurationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic29 3-Wire Serial I/O Mode Timing Communication operationSerial clock selection Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Relt CmdtData transfer order Start of transferMOV SIO, XA Wire serial I/O mode applicationsMOV XA, Tdata SCK SO/SB0MOV XA, Tdata XCH XA, SIO MOV XA, Tdata SIO, XAIecsi MOV RDATA, XACPU SB0 SCK SBI Mode Operation+ VDD SB0 SCKBusy signal Busy control function Address/command/data differentiation functionAcknowledge signal ACK control function SBI functionsSB0 C0 ACK Busy SBI definitionSB0 ACK SB0 D0 ACK BusySCK H Bus release signal RELCommand signal CMD SCK H SB0Address 37 Slave Selection by AddressCommand & data DataAcknowledge signal ACK SCK SB0 ACKSCK SB0 ACK Busy Busy signal BUSY, ready signal Ready100 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105SIO SCK SB0 Relt Cmdt Reld Cmdd RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK44 Ackt Operation 107When Acke = 1 interval is short When Acke is set after completion of transferWhen Acke = 0 on completion of transfer 108SCK SB0 ACK Ackd When ACK signal is output after 9th SCK clock interval109 SCK SB0 Bsye ACKSB0 ACK Ready 110 Signals in SBI ModeSCK Cmdd SB0 Ready111 REL CMDPin configuration Pin Configuration Diagram113 Address match detection methodUse of slave address register SVA Peripheral 114Chapter Hardware50 Command Transmission from Master Device to Slave 115116 51 Data Transmission from Master Device to Slave Device52 Data Transmission from Slave Device to Master Device 117Points to note concerning SBI mode 118119 SBI mode applicationSerial bus configuration 120 Description of commands Command typesIi Communication procedure ➁ WRITE, END and Stop commands Iii Command formats➀ Read command 121ACK Stop 122MSM Status ➂ Status command123 MSB LSB124 Reset command➄ Chgmst command ChgmstErrors generated on the master side Iv Error occurrenceErrors generated on the slave side 125Interrupt Functions 127 VEN T1 GOT OBT Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VENT1 Gotobt VENT2 GOTO0Example EI Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal IE0External interrupt input pin hardware 130INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise EliminationFB4H IM03 Interrupt master enable flag IME132 FB2H133 Interrupt status flagIST0 Interrupt Servicing Status IME=1 Interrupt Functions Interrupt SequenceYES Interrupt INTxxx generation 136 EI Iecsi Interrupt Functions Interrupt ApplicationsInterrupt enabling/disabling CLR1 IRQ0 Example using INTBT, INT0 falling edge active, and Intcsi138 ➄ Reti➂ Intcsi Reti 139EI IE0 ➃ EI Iecsi RetiINT0 Intcsi ➁ Reti Pending interrupt execution140 Standby Function Stop modeHalt mode Standby Function Standby Mode Setting and Operation States Standby Mode Operation StatesHalt mode reset by Reset input Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by interrupt generation144 HaltStandby Function Operation After Standby Mode Reset IME =Reset Signal Acceptance Reset at Power-onOFF State of Hardware after Reset147 Architecture and Memory MAP 148Stack Instructions Instruction SET Special InstructionsBit Manipulation Instructions Example A0Addc Base Correction InstructionsBase correction at addition Adds AddcOperation description legend Instruction SET Instruction SET and ITS OperationOperation identifier and description 152 Description of addressing area field symbolsDescription of machine cycle field Addc Movt XA, @PCXAAdds XOR154 155 Instruction GroupInstructions NOPBit manipulation addressing operation code Description of operation code symbolsInstruction SET Operation Code of Each Instruction Iebt Iecsi IE0 IE2Rorc Not Incs SET CLR SKT NotRET Rets Reti Push POP Halt Stop NOPMOV A, #0BH Instruction SET Instruction Functions and ApplicationMove Instructions MOV HL, #5FHMOV XA, 20H 160161 Loop XCHMOV XCH 162 Table Reference InstructionsTable data on that 02FFH163 Arithmetic and Logic InstructionsSee section Or A, @HL 164Rorc a 165Incs reg 166SKE reg, #n4 167Carry Flag Operation Instructions 168Bit Manipuration Instructions 169SKF mem. bit 170BR addr 171Subroutine Stack Control Instructions 172Push rp 173Interrupt Control Instructions 174Input/Output Instructions 175Halt 176177 178 179 Language ProcessorProm Writing Tools Debugging Tools 180IBM PC/AT Development Tool Configuration181 182 183 Pmgb Cmdd 184Irqcs Port