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NEC PD75402A, PD75P402 user manual Shift register data do not match Register data match

Models: PD75402A PD75P402

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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Signal from address comparator (R)

COI*

Clearing Conditions (COI = 0)	Setting Condition (COI = 1)

When slave address register (SVA) and	When slave address register (SVA) and shift
shift register data do not match.	register data match.

*A CIO read is valid only before the start of after completion of a serial transfer. During a transfer an indeterminate value will be read.

Also, COI data written by an 8-bit manipulation instruction is ignored.

Serial interface operation enable/disable specification bit (W)

		Shift Register	Serial Clock	IRQCSI Flag	SO/SB0 & SI Pins
		Operation	Counter	IRQCSI Flag	SO/SB0 & SI Pins
		Operation	Counter

	1	Shift operation	Count operation	Settable	Function in each
CSIE		Shift operation			mode plus port 0
CSIE		enabled			mode plus port 0
		enabled			function
					function

Page 97

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NEC PD75402A, PD75P402 user manual Shift register data do not match Register data match

Contents

ΜPD75402A Page Major Revisions in This Version Instruction Functions and Application Content to be read carefullyRemarks Development Tool Related Documents Related Documentation Device Related DocumentsOther Related Documents Latest documents should be used for design purposes, etcContents Interrupt Control Circuit Configuration Basic Interval TimerDigital INPUT/OUTPUT Ports Clock Generation CircuitStandby Mode Reset Standby Mode Setting and Operation StatesOperation After Standby Mode Reset Standby Mode ApplicationContents of Figures Fig. No Title Table No Title Contents of TablesFAX PPC GeneralECR VCR For details, see Interrupt Functions General Outline of FunctionsOrdering Information General Ordering Information and Quality GradeQuality Grade VPP PORT0 PORT1 PORT2 PORT3 PORT5 Block DiagramINT0 Interrupt INT2 Control PORT6SCK General PIN ConfigurationSO/SB0 VPP NCProm mode NC NC NC P50 2 44-Pin Plastic QFP 10mm Normal operating modeP01/SCK NC V SS NC P22/PCLA2 NC NC NC NC PIN Functions SCK ΜPD75402A PIN Function List Port Pin ListSO/SB0 INT0SCK SB0 Port 0’s, 1’s Dual-Function Pins PIN Functions Normal Operating Mode5 INT2 ..... Port 1 Dual-Function Input 4 INT0 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output 7 X1, X2 Crystal Reset ResetCE Chip Enable ..... Input PIN Functions Prom ModeOE Output Enable ..... Input 1 A0 to A14 Address ..... InputPin Input/output Types PIN Functions PIN INPUT/OUTPUT CircuitsRemarks a circle P22/PCLIN/OUT OUTType F B Type M a PIN Functions Unused PIN Treatment P00, ResetData Memory Bank Configuration Features of Architecture and Memory MAPFbfh FB0HFF0H Fffh @HL Addressing Mode ListBit direct addressing mem.bit Data Memory Addressing ModesBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit SUB Push POP RET Stack addressingPush HL POP Push HL Push XA RETApplicable Addressing Modes at Peripheral Hardware Operation Features of Architecture and Memory MAP MEMORY-MAPPED I/OΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Program Counter PC .... Bits Internal CPU FunctionsPC1 PC0 Program Memory Map Program Memory ROM .... ,920 Words × 8 BitsData area Internal CPU Functions Data Memory RAMGeneral register area Stack areaPeripheral hardware area Internal CPU Functions General Register .... × 4 Bits General Register ConfigurationAccumulators Internal CPU Functions AccumulatorRange of 020H to 03FH Internal CPU Functions Stack Pointer SP .... BitsMOV SP, XA SP4 SP3 SP2 SP1 SP0IST0 PSW Data Saved to Stack MemoryCarry flag CY Internal CPU Functions Program Status Word PSW .... BitsCarry Flag Manipulation Instructions SET1 Interrupt Status Flag Indication ContentSkip flag SK2, SK1, SK0 Interrupt status flag IST0PORT0 Peripheral Hardware FunctionsDigital Input/Output Port Types and Characteristics PO0 Csim PogaPO1 INT2 INT0PO3 Configuration of PortConfiguration of Ports 2 PM5 Pmgb Input/Output Mode SettingPmga Digital Input/Output Port Handling InstructionsFech PM5 PM2 Pmgb Bit handling instructions Operations when output mode is set Operations when input mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-up Resistors Internal Pull-Up Resistor Specification for Each PortPORT1 MOV POGA, XAFdch PO6 PO3 PO2 PO1 PO0 Data fetch by 2-machine-cycle instruction Digital Input/Output Port Input/Output TimingData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instructionPeripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit ConfigurationProcessor clock control register PCC Clock Generation Circuit Function and OperaionSEL MOV PCC, aPCC FB3H PCC3 PCC2 PCC1 PCC012 System Clock Oscillation Circuit External Circuitry System clock oscillation circuit13 Example of Poor Resonator Connection Circuit 2/2 Use of Variable Minimum Instruction Execution Time Function CPU Clock SettingExample Maximum Time Required for Change of CPU Clock 15 Change of Φ after Power-On ResetDifferences Between μPD75402A and μPD75402 FB3H PCC3 PCC2 PCC1 17 μPD75402 Processor Clock Control Register FormatPeripheral Hardware Functions Clock Output Circuit Clock Output Circuit ConfigurationP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clom Clock Output Mode Register ClomExamle of Remote Control Application Clock Output ProcedureBasic Interval Timer Configuration Peripheral Hardware Functions Basic Interval TimerMPX BTM3 BTM2MOV BTM. a Basic Intercal Timer Mode Register BTMBTM3 BTMFrom the beginning Basic Interval Timer OperationMOV BTM,A Examples of Basic Interval Timer ApplicationsIebt SEL MOVWire serial I/O mode Operation-halted modePeripheral Hardware Functions Serial Interface Serial Interface FunctionsSerial Interface Configuration SBI mode serial bus interface modeFunctions Serial Interface Block DiagramSerial bus interface control register Sbic Serial operating mode register CsimShift register SIO SO latchIntcsi control circuit Register Functions Serial operating mode register CsimSerial clock control circuit Serial clock selection bit W Serial interface operating mode selection bit WCsie COI WUP CSIM3 CSIM1 Csim Csie Signal from address comparator RSET1 Csie MOV CSIM, XACsie CSIM3 Csie CSIM1Cmdd Reld Cmdt Relt FE2HCommand detection flag R Command trigger bit WBus release detection flag R Acknowledge trigger bit WAcknowledge detection flag R Busy enable bit R/WCLK SIOBUSY/ACK See 5.5.6 8 Error detection for details Error detectionSlave address register SVA Slave address detectionCsie C0I WUP CSIM3 CSIM1 Csim Register setting28 Example of 3-Wire Serial I/O System Configuration 5 3-Wire Serial I/O Mode OperationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic Command trigger bitCommunication operation 29 3-Wire Serial I/O Mode TimingSignals Serial Clock Selection and Use in 3-Wire Serial I/O ModeSerial clock selection Relt CmdtStart of transfer Data transfer orderMOV XA, Tdata Wire serial I/O mode applicationsMOV SIO, XA SCK SO/SB0Iecsi MOV XA, Tdata SIO, XAMOV XA, Tdata XCH XA, SIO MOV RDATA, XA+ VDD SBI Mode OperationCPU SB0 SCK SB0 SCKAcknowledge signal ACK control function Address/command/data differentiation functionBusy signal Busy control function SBI functionsSB0 ACK SBI definitionSB0 C0 ACK Busy SB0 D0 ACK BusyCommand signal CMD Bus release signal RELSCK H SCK H SB037 Slave Selection by Address AddressData Command & dataSCK SB0 ACK Acknowledge signal ACK100 Busy signal BUSY, ready signal ReadySCK SB0 ACK Busy 101 102 103 104 105 Serial Clock Selection and Use in SBI Mode106 RELT, CMDT, Reld & Cmdd Operation SlaveSIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK107 44 Ackt OperationWhen Acke = 0 on completion of transfer When Acke is set after completion of transferWhen Acke = 1 interval is short 108109 When ACK signal is output after 9th SCK clock intervalSCK SB0 ACK Ackd SCK SB0 Bsye ACKSCK Cmdd 110 Signals in SBI ModeSB0 ACK Ready SB0 ReadyREL CMD 111Pin Configuration Diagram Pin configurationUse of slave address register SVA Address match detection method113 Chapter 114Peripheral Hardware115 50 Command Transmission from Master Device to Slave51 Data Transmission from Master Device to Slave Device 116117 52 Data Transmission from Slave Device to Master Device118 Points to note concerning SBI modeSerial bus configuration SBI mode application119 Ii Communication procedure Description of commands Command types120 ➀ Read command Iii Command formats➁ WRITE, END and Stop commands 121MSM 122ACK Stop 123 ➂ Status commandStatus MSB LSB➄ Chgmst command Reset command124 ChgmstErrors generated on the slave side Iv Error occurrenceErrors generated on the master side 125Interrupt Functions 127 Interrupt Request Source Types Interrupt Functions Interrupt Source Types and Vector TableVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0Interrupt Request Flag Setting Signal Interrupt request flag & interrupt enable flagExample EI IE0130 External interrupt input pin hardwareINT2 Input Noise Elimination INT0 Noise Elimination Circuit Input/Output Timing132 Interrupt master enable flag IMEFB4H IM03 FB2HIST0 Interrupt Servicing Status Interrupt status flag133 YES Interrupt Functions Interrupt SequenceIME=1 Interrupt INTxxx generation 136 Interrupt enabling/disabling Interrupt Functions Interrupt ApplicationsEI Iecsi 138 Example using INTBT, INT0 falling edge active, and IntcsiCLR1 IRQ0 ➄ RetiEI IE0 139➂ Intcsi Reti ➃ EI Iecsi Reti140 Pending interrupt executionINT0 Intcsi ➁ Reti Halt mode Stop modeStandby Function Standby Mode Operation States Standby Function Standby Mode Setting and Operation StatesStop mode reset by Reset input Standby Function Standby Mode ResetHalt mode reset by Reset input Halt mode reset by interrupt generationHalt 144IME = Standby Function Operation After Standby Mode ResetReset at Power-on Reset Signal Acceptance147 State of Hardware after ResetOFF 148 Architecture and Memory MAPBit Manipulation Instructions Instruction SET Special InstructionsStack Instructions Example A0Base correction at addition Base Correction InstructionsAddc Adds AddcOperation identifier and description Instruction SET Instruction SET and ITS OperationOperation description legend Description of machine cycle field Description of addressing area field symbols152 Adds Movt XA, @PCXAAddc XOR154 Instructions Instruction Group155 NOPInstruction SET Operation Code of Each Instruction Description of operation code symbolsBit manipulation addressing operation code Iebt Iecsi IE0 IE2SET CLR SKT Not Rorc Not IncsHalt Stop NOP RET Rets Reti Push POPMove Instructions Instruction SET Instruction Functions and ApplicationMOV A, #0BH MOV HL, #5FH160 MOV XA, 20HMOV XCH Loop XCH161 Table data on that Table Reference Instructions162 02FFHSee section Arithmetic and Logic Instructions163 164 Or A, @HL165 Rorc a166 Incs reg167 SKE reg, #n4168 Carry Flag Operation Instructions169 Bit Manipuration Instructions170 SKF mem. bit171 BR addr172 Subroutine Stack Control Instructions173 Push rp174 Interrupt Control Instructions175 Input/Output Instructions176 Halt177 178 Prom Writing Tools Language Processor179 180 Debugging Tools181 Development Tool ConfigurationIBM PC/AT 182 183 Irqcs 184Pmgb Cmdd Port

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Signal from address comparator (R)

shift register data do not match.

register data match.

CSIE