Serial bus interface control register Sbic, 103 | NEC PD75P402

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(b) Serial bus interface control register (SBIC)

When the SBI mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC).

SBIC is manipulated by bit manipulation instructions.

Reset input clears the SBIC register to 00H.

The shaded area indicates bits used in the SBI mode.

Address

7

6

5

4

3

2

1

0

Symbol

FE2H

BSYE

ACKD

ACKE

ACKT

CMDD

RELD

CMDT

RELT

SBIC

Bus Release Trigger Bit (W)

Command Trigger Bit (W)

Bus Release Datection Flag (R)

Command Detection Flag (R)

Acknowledge Trigger Bit (W)

Acknowledge Enable Bit (R/W)

Acknowledge Detection Flag (R)

Busy Enable Bit (R/W)

Remarks (R) Read only

(W)Write only

(R/W) Read/write enabled

Bus release trigger bit (W)

RELT

The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this bit (RELT = 1), after which the RELT bit is automatically cleared (0).

Note SB0 must not be set during a serial transfer: Ensure that it is set before a transfer is started or after it is completed.

Command trigger bit (W)

CMDT

The command signal (CMD) trigger output control bit. The SO latch is cleared (0) by setting this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).

Note SB0 must not be set during a serial transfer: Ensure that it is set before a transfer is started or after it is completed.

103

Image 114

NEC PD75P402, PD75402A user manual Serial bus interface control register Sbic, 103

Contents

ΜPD75402A Page Major Revisions in This Version Content to be read carefully Instruction Functions and ApplicationRemarks Other Related Documents Related Documentation Device Related DocumentsDevelopment Tool Related Documents Latest documents should be used for design purposes, etc Contents Digital INPUT/OUTPUT Ports Basic Interval TimerInterrupt Control Circuit Configuration Clock Generation Circuit Operation After Standby Mode Reset Standby Mode Setting and Operation StatesStandby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Contents of Tables Table No Title General FAX PPCECR VCR General Outline of Functions For details, see Interrupt Functions General Ordering Information and Quality Grade Ordering InformationQuality Grade VPP INT0 Interrupt INT2 Control Block DiagramPORT0 PORT1 PORT2 PORT3 PORT5 PORT6 SO/SB0 General PIN ConfigurationSCK VPP NC Prom mode P01/SCK 2 44-Pin Plastic QFP 10mm Normal operating modeNC NC NC P50 NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions SO/SB0 ΜPD75402A PIN Function List Port Pin ListSCK INT0 SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function Pins 4 INT0 ..... Port 1 Dual-Function Input 5 INT2 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output Reset Reset 7 X1, X2 Crystal OE Output Enable ..... Input PIN Functions Prom ModeCE Chip Enable ..... Input 1 A0 to A14 Address ..... Input Remarks a circle PIN Functions PIN INPUT/OUTPUT CircuitsPin Input/output Types P22/PCL OUT IN/OUT Type F B Type M a P00, Reset PIN Functions Unused PIN Treatment Features of Architecture and Memory MAP Data Memory Bank Configuration FB0H FbfhFF0H Fffh Addressing Mode List @HL Data Memory Addressing Modes Bit direct addressing mem.bitBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Push HL POP Stack addressingSUB Push POP RET Push HL Push XA RET Features of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware Operation ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Internal CPU Functions Program Counter PC .... BitsPC1 PC0 Program Memory ROM .... ,920 Words × 8 Bits Program Memory Map General register area Internal CPU Functions Data Memory RAMData area Stack area Peripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 Bits Internal CPU Functions Accumulator Accumulators MOV SP, XA Internal CPU Functions Stack Pointer SP .... BitsRange of 020H to 03FH SP4 SP3 SP2 SP1 SP0 Data Saved to Stack Memory IST0 PSW Internal CPU Functions Program Status Word PSW .... Bits Carry flag CYCarry Flag Manipulation Instructions Skip flag SK2, SK1, SK0 Interrupt Status Flag Indication ContentSET1 Interrupt status flag IST0 Peripheral Hardware Functions PORT0 Digital Input/Output Port Types and Characteristics PO1 Csim PogaPO0 INT2 INT0 Configuration of Port PO3 Configuration of Ports 2 Input/Output Mode Setting PM5 Pmgb Digital Input/Output Port Handling Instructions PmgaFech PM5 PM2 Pmgb Bit handling instructions Operations when input mode is set Operations when output mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up Resistors MOV POGA, XA PORT1Fdch PO6 PO3 PO2 PO1 PO0 Data latching by 1-machine-cycle instruction Digital Input/Output Port Input/Output TimingData fetch by 2-machine-cycle instruction Data latching by 2-machine-cycle instruction Clock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation Circuit SEL Clock Generation Circuit Function and OperaionProcessor clock control register PCC MOV PCC, a FB3H PCC3 PCC2 PCC1 PCC0 PCC System clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry 13 Example of Poor Resonator Connection Circuit 2/2 CPU Clock Setting Use of Variable Minimum Instruction Execution Time FunctionExample 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU Clock Differences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1 Clock Output Circuit Configuration Peripheral Hardware Functions Clock Output CircuitP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Mode Register Clom Clom Clock Output Procedure Examle of Remote Control Application MPX Peripheral Hardware Functions Basic Interval TimerBasic Interval Timer Configuration BTM3 BTM2 BTM3 Basic Intercal Timer Mode Register BTMMOV BTM. a BTM Basic Interval Timer Operation From the beginning Iebt Examples of Basic Interval Timer ApplicationsMOV BTM,A SEL MOV Peripheral Hardware Functions Serial Interface Operation-halted modeWire serial I/O mode Serial Interface Functions SBI mode serial bus interface mode Serial Interface Configuration Serial Interface Block Diagram Functions Shift register SIO Serial operating mode register CsimSerial bus interface control register Sbic SO latch Register Functions Serial operating mode register Csim Intcsi control circuitSerial clock control circuit Serial interface operating mode selection bit W Serial clock selection bit WCsie COI WUP CSIM3 CSIM1 Csim Signal from address comparator R Csie Csie CSIM3 MOV CSIM, XASET1 Csie Csie CSIM1 FE2H Cmdd Reld Cmdt Relt Bus release detection flag R Command trigger bit WCommand detection flag R Acknowledge trigger bit W Busy enable bit R/W Acknowledge detection flag R SIO CLKBUSY/ACK Slave address register SVA Error detectionSee 5.5.6 8 Error detection for details Slave address detection Register setting Csie C0I WUP CSIM3 CSIM1 Csim 5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System Configuration Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic 29 3-Wire Serial I/O Mode Timing Communication operation Serial clock selection Serial Clock Selection and Use in 3-Wire Serial I/O ModeSignals Relt Cmdt Data transfer order Start of transfer MOV SIO, XA Wire serial I/O mode applicationsMOV XA, Tdata SCK SO/SB0 MOV XA, Tdata XCH XA, SIO MOV XA, Tdata SIO, XAIecsi MOV RDATA, XA CPU SB0 SCK SBI Mode Operation+ VDD SB0 SCK Busy signal Busy control function Address/command/data differentiation functionAcknowledge signal ACK control function SBI functions SB0 C0 ACK Busy SBI definitionSB0 ACK SB0 D0 ACK Busy SCK H Bus release signal RELCommand signal CMD SCK H SB0 Address 37 Slave Selection by Address Command & data Data Acknowledge signal ACK SCK SB0 ACK Busy signal BUSY, ready signal Ready 100SCK SB0 ACK Busy 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105 SIO SCK SB0 Relt Cmdt Reld Cmdd RELT, CMDT, Reld & Cmdd Operation Slave106 SIO SCK 44 Ackt Operation 107 When Acke = 1 interval is short When Acke is set after completion of transferWhen Acke = 0 on completion of transfer 108 SCK SB0 ACK Ackd When ACK signal is output after 9th SCK clock interval109 SCK SB0 Bsye ACK SB0 ACK Ready 110 Signals in SBI ModeSCK Cmdd SB0 Ready 111 REL CMD Pin configuration Pin Configuration Diagram Address match detection method Use of slave address register SVA113 Peripheral 114Chapter Hardware 50 Command Transmission from Master Device to Slave 115 116 51 Data Transmission from Master Device to Slave Device 52 Data Transmission from Slave Device to Master Device 117 Points to note concerning SBI mode 118 SBI mode application Serial bus configuration119 Description of commands Command types Ii Communication procedure120 ➁ WRITE, END and Stop commands Iii Command formats➀ Read command 121 122 MSMACK Stop Status ➂ Status command123 MSB LSB 124 Reset command➄ Chgmst command Chgmst Errors generated on the master side Iv Error occurrenceErrors generated on the slave side 125 Interrupt Functions 127 VEN T1 GOT OBT Interrupt Functions Interrupt Source Types and Vector TableInterrupt Request Source Types VENT1 Gotobt VENT2 GOTO0 Example EI Interrupt request flag & interrupt enable flagInterrupt Request Flag Setting Signal IE0 External interrupt input pin hardware 130 INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise Elimination FB4H IM03 Interrupt master enable flag IME132 FB2H Interrupt status flag IST0 Interrupt Servicing Status133 Interrupt Functions Interrupt Sequence YESIME=1 Interrupt INTxxx generation 136 Interrupt Functions Interrupt Applications Interrupt enabling/disablingEI Iecsi CLR1 IRQ0 Example using INTBT, INT0 falling edge active, and Intcsi138 ➄ Reti ➂ Intcsi Reti 139EI IE0 ➃ EI Iecsi Reti Pending interrupt execution 140INT0 Intcsi ➁ Reti Stop mode Halt modeStandby Function Standby Function Standby Mode Setting and Operation States Standby Mode Operation States Halt mode reset by Reset input Standby Function Standby Mode ResetStop mode reset by Reset input Halt mode reset by interrupt generation 144 Halt Standby Function Operation After Standby Mode Reset IME = Reset Signal Acceptance Reset at Power-on State of Hardware after Reset 147OFF Architecture and Memory MAP 148 Stack Instructions Instruction SET Special InstructionsBit Manipulation Instructions Example A0 Addc Base Correction InstructionsBase correction at addition Adds Addc Instruction SET Instruction SET and ITS Operation Operation identifier and descriptionOperation description legend Description of addressing area field symbols Description of machine cycle field152 Addc Movt XA, @PCXAAdds XOR 154 155 Instruction GroupInstructions NOP Bit manipulation addressing operation code Description of operation code symbolsInstruction SET Operation Code of Each Instruction Iebt Iecsi IE0 IE2 Rorc Not Incs SET CLR SKT Not RET Rets Reti Push POP Halt Stop NOP MOV A, #0BH Instruction SET Instruction Functions and ApplicationMove Instructions MOV HL, #5FH MOV XA, 20H 160 Loop XCH MOV XCH161 162 Table Reference InstructionsTable data on that 02FFH Arithmetic and Logic Instructions See section163 Or A, @HL 164 Rorc a 165 Incs reg 166 SKE reg, #n4 167 Carry Flag Operation Instructions 168 Bit Manipuration Instructions 169 SKF mem. bit 170 BR addr 171 Subroutine Stack Control Instructions 172 Push rp 173 Interrupt Control Instructions 174 Input/Output Instructions 175 Halt 176 177 178 Language Processor Prom Writing Tools179 Debugging Tools 180 Development Tool Configuration 181IBM PC/AT 182 183 Pmgb Cmdd 184Irqcs Port