NEC PD75P402, PD75402A user manual 111, Rel Cmd

Table 5-8 Signals in SBI Mode

(2/2)

Signal Name

Output

Definition

Timing Chart

Output

Effect on

Meaning of

Device

Condition

Flag

Signal

Serial Clock

Master

Synchronization clock for

Exection of

IRQCSI set

Timing of signal output

output of address/command/

instruction

(rise of 9th

to serial data bus

(SCK)

data,

ACK

signal,

to write to

SCK

clock

SCK

1

2

7

8

9

10

Synchronous

BUSY

signal,

SIO when

cycle) *1

etc.

SB0

CSIE = 1

Address/command/ data is

(serial

transferred in first 8 cycles.

transfer

start

Address

Master

8-bit data transferred in

SCK

1

2

7

8

Address value of slave

(A7 to A0)

synchronization with

device on serial bus

SCK

directive) *2

after REL signl and CMD

SB0

signal output.

REL

CMD

Master

8-bit data transferred in

Directive, meddage,

SCK

1

2

7

8

Command

synchronization with

SCK

etc., to slave device.

(C7 to C0)

after CMD signal only is

output without output of REL

SB0

signal.

CMD

Data

Master/

8-bit data transferred in

Data to ve processed by

(D7 to D0)

slave

synchronization with SCK

slave or master device

with no output of either REL

SCK

1

2

7

8

signal or CMD signal.

SB0

*1. When WUP = 0, IRQCSI is always set on the 9th rise of SCK.

When WUP = 1, IRQCSI is set on the 9th rise of SCK only with an address is receive and that address matches the value of the slave address register (SVA).

2.In data transmission/reception, when in the BUSY stare, the transfer starts after transition to the READY state.

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

111