NEC PD75P402 Serial clock selection, Serial Clock Selection and Use in 3-Wire Serial I/O Mode

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

(3) Serial clock selection

Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the

following clocks can be selected.

Table 5-6 Serial Clock Selection and Use (in 3-Wire Serial I/O Mode)

Mode		Serial Clock		Possible Timing for Shift
Register
				Register R/W and Serial	Use
CSIM 1	Source		Serial Clock	Transfer Start
			Masking
0	External		Automatically	Possible only when serial transfer	Slave CPU
			masked at end of
	SCK			is halted* or when SCK is high.
			8-bit data
1	fXX/24		transfer.	Possible only when serial transfer	Medium-speed
				is halted* or when SCK is high.	serial transfer

*“When serial transfer is halted” means in the operation-halted mode, or when the serial clock is masked after an 8-bit transfer.

(4) Signals

RELT and CMDT operation is shown in Fig. 5-30.

Fig. 5-30 RELT & CMDT Operation

SO

RELT

CMDT

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