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NEC PD75P402, PD75402A user manual Data Transmission from Slave Device to Master Device, 117

Models: PD75402A PD75P402

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Fig. 5-52 Data Transmission from Slave Device to Master Device ★

Master Device Processing (Reception Side)

Program		FFH Write
Processing		to SIO

SIO ACKT Read Setting

FFH Write to SIO

Receive Data Processing

Hardware

SCK

Serial Receive Operation

IRQCSI

ACK

Serial

Operation

Stop-

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Output

Reception

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Transfer Line

CHAPTER

SCK Pin

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PERIPHERAL

SB0 Pin

BUSY

READY

D7

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D1

D0

ACK

BUSY

D7

D6

READY

Data

HARDWARE

Slave Device Processing (Transmission Side)

Program

Write

Write

to

to

Processing

SIO

SIO

FUNCTIONS

Hardware

BUSY

Serial Transmit Operation

IRQCSI

ACKD

BUSY

BUSY

Operation

Clear-

Genera-

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NEC PD75P402, PD75402A user manual Data Transmission from Slave Device to Master Device, 117

Contents

ΜPD75402A Page Major Revisions in This Version Remarks Content to be read carefullyInstruction Functions and Application Related Documentation Device Related Documents Development Tool Related DocumentsOther Related Documents Latest documents should be used for design purposes, etcContents Basic Interval Timer Interrupt Control Circuit ConfigurationDigital INPUT/OUTPUT Ports Clock Generation CircuitStandby Mode Setting and Operation States Standby Mode ResetOperation After Standby Mode Reset Standby Mode ApplicationContents of Figures Fig. No Title Contents of Tables Table No TitleECR VCR GeneralFAX PPC General Outline of Functions For details, see Interrupt FunctionsQuality Grade General Ordering Information and Quality GradeOrdering Information VPP Block Diagram PORT0 PORT1 PORT2 PORT3 PORT5INT0 Interrupt INT2 Control PORT6General PIN Configuration SCKSO/SB0 VPP NCProm mode 2 44-Pin Plastic QFP 10mm Normal operating mode NC NC NC P50P01/SCK NC V SS NC P22/PCLA2 NC NC NC NC PIN Functions ΜPD75402A PIN Function List Port Pin List SCKSO/SB0 INT0SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function PinsPCL ..... Port 2 Dual-Function Output 4 INT0 ..... Port 1 Dual-Function Input5 INT2 ..... Port 1 Dual-Function Input Reset Reset 7 X1, X2 CrystalPIN Functions Prom Mode CE Chip Enable ..... InputOE Output Enable ..... Input 1 A0 to A14 Address ..... InputPIN Functions PIN INPUT/OUTPUT Circuits Pin Input/output TypesRemarks a circle P22/PCLOUT IN/OUTType F B Type M a P00, Reset PIN Functions Unused PIN TreatmentFeatures of Architecture and Memory MAP Data Memory Bank ConfigurationFF0H Fffh FB0HFbfh Addressing Mode List @HLBit direct addressing mem Data Memory Addressing ModesBit direct addressing mem.bit Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Stack addressing SUB Push POP RETPush HL POP Push HL Push XA RETFeatures of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware OperationΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 PC1 PC0 Internal CPU FunctionsProgram Counter PC .... Bits Program Memory ROM .... ,920 Words × 8 Bits Program Memory MapInternal CPU Functions Data Memory RAM Data areaGeneral register area Stack areaPeripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 BitsInternal CPU Functions Accumulator AccumulatorsInternal CPU Functions Stack Pointer SP .... Bits Range of 020H to 03FHMOV SP, XA SP4 SP3 SP2 SP1 SP0Data Saved to Stack Memory IST0 PSWCarry Flag Manipulation Instructions Internal CPU Functions Program Status Word PSW .... BitsCarry flag CY Interrupt Status Flag Indication Content SET1Skip flag SK2, SK1, SK0 Interrupt status flag IST0Peripheral Hardware Functions PORT0Digital Input/Output Port Types and Characteristics Csim Poga PO0PO1 INT2 INT0Configuration of Port PO3Configuration of Ports 2 Input/Output Mode Setting PM5 PmgbFech PM5 PM2 Pmgb Digital Input/Output Port Handling InstructionsPmga Bit handling instructions Digital Input/Output Port Operations Operations when input mode is setOperations when output mode is set Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up ResistorsFdch PO6 PO3 PO2 PO1 PO0 MOV POGA, XAPORT1 Digital Input/Output Port Input/Output Timing Data fetch by 2-machine-cycle instructionData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instructionClock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation CircuitClock Generation Circuit Function and Operaion Processor clock control register PCCSEL MOV PCC, aFB3H PCC3 PCC2 PCC1 PCC0 PCCSystem clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry13 Example of Poor Resonator Connection Circuit 2/2 Example CPU Clock SettingUse of Variable Minimum Instruction Execution Time Function 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU ClockDifferences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1P22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Circuit ConfigurationPeripheral Hardware Functions Clock Output Circuit Clock Output Mode Register Clom ClomClock Output Procedure Examle of Remote Control ApplicationPeripheral Hardware Functions Basic Interval Timer Basic Interval Timer ConfigurationMPX BTM3 BTM2Basic Intercal Timer Mode Register BTM MOV BTM. aBTM3 BTMBasic Interval Timer Operation From the beginningExamples of Basic Interval Timer Applications MOV BTM,AIebt SEL MOVOperation-halted mode Wire serial I/O modePeripheral Hardware Functions Serial Interface Serial Interface FunctionsSBI mode serial bus interface mode Serial Interface ConfigurationSerial Interface Block Diagram FunctionsSerial operating mode register Csim Serial bus interface control register SbicShift register SIO SO latchSerial clock control circuit Register Functions Serial operating mode register CsimIntcsi control circuit Csie COI WUP CSIM3 CSIM1 Csim Serial interface operating mode selection bit WSerial clock selection bit W Signal from address comparator R CsieMOV CSIM, XA SET1 CsieCsie CSIM3 Csie CSIM1FE2H Cmdd Reld Cmdt ReltCommand trigger bit W Command detection flag RBus release detection flag R Acknowledge trigger bit WBusy enable bit R/W Acknowledge detection flag RBUSY/ACK SIOCLK Error detection See 5.5.6 8 Error detection for detailsSlave address register SVA Slave address detectionRegister setting Csie C0I WUP CSIM3 CSIM1 Csim5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System ConfigurationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic29 3-Wire Serial I/O Mode Timing Communication operationSerial Clock Selection and Use in 3-Wire Serial I/O Mode SignalsSerial clock selection Relt CmdtData transfer order Start of transferWire serial I/O mode applications MOV XA, TdataMOV SIO, XA SCK SO/SB0MOV XA, Tdata SIO, XA IecsiMOV XA, Tdata XCH XA, SIO MOV RDATA, XASBI Mode Operation + VDDCPU SB0 SCK SB0 SCKAddress/command/data differentiation function Acknowledge signal ACK control functionBusy signal Busy control function SBI functionsSBI definition SB0 ACKSB0 C0 ACK Busy SB0 D0 ACK BusyBus release signal REL Command signal CMDSCK H SCK H SB0Address 37 Slave Selection by AddressCommand & data DataAcknowledge signal ACK SCK SB0 ACKSCK SB0 ACK Busy Busy signal BUSY, ready signal Ready100 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105RELT, CMDT, Reld & Cmdd Operation Slave 106SIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK44 Ackt Operation 107When Acke is set after completion of transfer When Acke = 0 on completion of transferWhen Acke = 1 interval is short 108When ACK signal is output after 9th SCK clock interval 109SCK SB0 ACK Ackd SCK SB0 Bsye ACK110 Signals in SBI Mode SCK CmddSB0 ACK Ready SB0 Ready111 REL CMDPin configuration Pin Configuration Diagram113 Address match detection methodUse of slave address register SVA 114 ChapterPeripheral Hardware50 Command Transmission from Master Device to Slave 115116 51 Data Transmission from Master Device to Slave Device52 Data Transmission from Slave Device to Master Device 117Points to note concerning SBI mode 118119 SBI mode applicationSerial bus configuration 120 Description of commands Command typesIi Communication procedure Iii Command formats ➀ Read command➁ WRITE, END and Stop commands 121ACK Stop 122MSM ➂ Status command 123Status MSB LSBReset command ➄ Chgmst command124 ChgmstIv Error occurrence Errors generated on the slave sideErrors generated on the master side 125Interrupt Functions 127 Interrupt Functions Interrupt Source Types and Vector Table Interrupt Request Source TypesVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0Interrupt request flag & interrupt enable flag Interrupt Request Flag Setting SignalExample EI IE0External interrupt input pin hardware 130INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise EliminationInterrupt master enable flag IME 132FB4H IM03 FB2H133 Interrupt status flagIST0 Interrupt Servicing Status IME=1 Interrupt Functions Interrupt SequenceYES Interrupt INTxxx generation 136 EI Iecsi Interrupt Functions Interrupt ApplicationsInterrupt enabling/disabling Example using INTBT, INT0 falling edge active, and Intcsi 138CLR1 IRQ0 ➄ Reti139 EI IE0➂ Intcsi Reti ➃ EI Iecsi RetiINT0 Intcsi ➁ Reti Pending interrupt execution140 Standby Function Stop modeHalt mode Standby Function Standby Mode Setting and Operation States Standby Mode Operation StatesStandby Function Standby Mode Reset Stop mode reset by Reset inputHalt mode reset by Reset input Halt mode reset by interrupt generation144 HaltStandby Function Operation After Standby Mode Reset IME =Reset Signal Acceptance Reset at Power-onOFF State of Hardware after Reset147 Architecture and Memory MAP 148Instruction SET Special Instructions Bit Manipulation InstructionsStack Instructions Example A0Base Correction Instructions Base correction at additionAddc Adds AddcOperation description legend Instruction SET Instruction SET and ITS OperationOperation identifier and description 152 Description of addressing area field symbolsDescription of machine cycle field Movt XA, @PCXA AddsAddc XOR154 Instruction Group Instructions155 NOPDescription of operation code symbols Instruction SET Operation Code of Each InstructionBit manipulation addressing operation code Iebt Iecsi IE0 IE2Rorc Not Incs SET CLR SKT NotRET Rets Reti Push POP Halt Stop NOPInstruction SET Instruction Functions and Application Move InstructionsMOV A, #0BH MOV HL, #5FHMOV XA, 20H 160161 Loop XCHMOV XCH Table Reference Instructions Table data on that162 02FFH163 Arithmetic and Logic InstructionsSee section Or A, @HL 164Rorc a 165Incs reg 166SKE reg, #n4 167Carry Flag Operation Instructions 168Bit Manipuration Instructions 169SKF mem. bit 170BR addr 171Subroutine Stack Control Instructions 172Push rp 173Interrupt Control Instructions 174Input/Output Instructions 175Halt 176177 178 179 Language ProcessorProm Writing Tools Debugging Tools 180IBM PC/AT Development Tool Configuration181 182 183 184 IrqcsPmgb Cmdd Port