NEC PD75402A, PD75P402 user manual Peripheral Hardware Functions Clock Generation Circuit

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

5.2CLOCK GENERATION CIRCUIT

The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the

operating mode of the CPU.

5.2.1Clock Generation Circuit Configuration

The configuration of the clock generation circuit is shown in Fig. 5-10.

★ Fig. 5-10 Clock Generation Circuit Block Diagram

• Basic Interva Timer (BT)

• Clock Output Circuit

• Serial Interface

• INT0 Noise Eliminator

• Clock Output Circuit

X1

VDD

		System	fXX or fX	1/16 to 1/512
		Clock
		Oscillation		Frequency Divider
		Circuit		1/2 1/16
		X2
		STOP		Selector	Frequency
		Oscillation
					Divider
					1/4	Φ￿
		PCC				• CPU
						• INT0 Noise
		PCC0				Eliminator
						• Clock Output
						Circuit
		PCC1
Bus	4			HALT F/F
		PCC2
				S
Internal	HALT*
		PCC3
	STOP*			R	Q
		Clear
		all bits
					RESET Input Rising Edge
	Clear	STOP F/F			Detection Signal
	PCC2	Q	S
					RESET Input Falling Edga
					Detection Signal
			R
					Standby Release Signal from
					Interrupt Control Circuit

Remarks 1.	fXX = System clock frequency
2.	fX = External clock frequency
3.	PCC: Processor clock control register
4.	1 clock cyck (fCY) of Φ is 1 machine cycle of an instruction.

* Instruction execution

54