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NEC PD75P402 Instruction SET Special Instructions, Bit Manipulation Instructions, Example A0

Models: PD75402A PD75P402

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CHAPTER 9. INSTRUCTION SET

9.1SPECIAL INSTRUCTIONS

This section outlines the special instructions of the μPD75402A instruction set.

9.1.1Bit Manipulation Instructions

μPD75402A bit manipulation can be performed by various instructions, such as the following:

(a)	Bit set	:	SET1	mem. bit
			SET1	fmem. bit
(b)	Bit clear:		CLR1	mem. bit
			CLR1	fmem. bit
(c)	Bit test	:	SKT	mem. bit
			SKT	fmem. bit
(d)	Bit test	:	SKF	mem. bit
			SKF	fmem. bit
(e)	Bit test & clear :		SKTCLR	fmem. bit
(f)	Boolean operation:		AND1	CY, fmem. bit
			OR1	CY, fmem. bit
			XOR1	CY, fmem. bit

fmem. bit is the bit address specified by special address bit manipulation addressing.

Especially, since I/O ports can always use all the bit manipulation instructions above, I/O port operation can be performed very efficiently.

9.1.2Stack Instructions

The following two kinds of stack instructions are available with the μPD75402A.

(a)MOV A, #n4 or MOV XA, #n8

(b)MOV HL, #n8

“Stack” signifies that these two kinds of instructions are placed in contiguous addresses.

Example A0 :	MOV	A,	#0
A1 :	MOV	A,	#1
XA7:	MOV	XA,	#07

When stack instructions are stacked such as in the example above, when the address executed first is A0, it is executed by replacing the next two instructions with NOP instructions. When the address executed first is A1, it is executed by replacing the next instruction with an NOP instruction. That is, only the instruction executed first is effective, all the stack instructions following it are processed as NOP instructions.

Constants can be efficiently set to accumulator (A register, register pair XA) and data pointer (register pair HL) by using these stack instructions.

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NEC PD75P402, PD75402A Instruction SET Special Instructions, Bit Manipulation Instructions, Stack Instructions, Example A0

Contents

ΜPD75402A Page Major Revisions in This Version Instruction Functions and Application Content to be read carefullyRemarks Related Documentation Device Related Documents Development Tool Related DocumentsOther Related Documents Latest documents should be used for design purposes, etcContents Basic Interval Timer Interrupt Control Circuit ConfigurationDigital INPUT/OUTPUT Ports Clock Generation CircuitStandby Mode Setting and Operation States Standby Mode ResetOperation After Standby Mode Reset Standby Mode ApplicationContents of Figures Fig. No Title Contents of Tables Table No TitleFAX PPC GeneralECR VCR General Outline of Functions For details, see Interrupt FunctionsOrdering Information General Ordering Information and Quality GradeQuality Grade VPP Block Diagram PORT0 PORT1 PORT2 PORT3 PORT5INT0 Interrupt INT2 Control PORT6General PIN Configuration SCKSO/SB0 VPP NCProm mode 2 44-Pin Plastic QFP 10mm Normal operating mode NC NC NC P50P01/SCK NC V SS NC P22/PCLA2 NC NC NC NC PIN Functions ΜPD75402A PIN Function List Port Pin List SCKSO/SB0 INT0SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function Pins5 INT2 ..... Port 1 Dual-Function Input 4 INT0 ..... Port 1 Dual-Function InputPCL ..... Port 2 Dual-Function Output Reset Reset 7 X1, X2 CrystalPIN Functions Prom Mode CE Chip Enable ..... InputOE Output Enable ..... Input 1 A0 to A14 Address ..... InputPIN Functions PIN INPUT/OUTPUT Circuits Pin Input/output TypesRemarks a circle P22/PCLOUT IN/OUTType F B Type M a P00, Reset PIN Functions Unused PIN TreatmentFeatures of Architecture and Memory MAP Data Memory Bank ConfigurationFbfh FB0HFF0H Fffh Addressing Mode List @HLBit direct addressing mem.bit Data Memory Addressing ModesBit direct addressing mem Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Stack addressing SUB Push POP RETPush HL POP Push HL Push XA RETFeatures of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware OperationΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 Program Counter PC .... Bits Internal CPU FunctionsPC1 PC0 Program Memory ROM .... ,920 Words × 8 Bits Program Memory MapInternal CPU Functions Data Memory RAM Data areaGeneral register area Stack areaPeripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 BitsInternal CPU Functions Accumulator AccumulatorsInternal CPU Functions Stack Pointer SP .... Bits Range of 020H to 03FHMOV SP, XA SP4 SP3 SP2 SP1 SP0Data Saved to Stack Memory IST0 PSWCarry flag CY Internal CPU Functions Program Status Word PSW .... BitsCarry Flag Manipulation Instructions Interrupt Status Flag Indication Content SET1Skip flag SK2, SK1, SK0 Interrupt status flag IST0Peripheral Hardware Functions PORT0Digital Input/Output Port Types and Characteristics Csim Poga PO0PO1 INT2 INT0Configuration of Port PO3Configuration of Ports 2 Input/Output Mode Setting PM5 PmgbPmga Digital Input/Output Port Handling InstructionsFech PM5 PM2 Pmgb Bit handling instructions Operations when output mode is set Operations when input mode is setDigital Input/Output Port Operations Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up ResistorsPORT1 MOV POGA, XAFdch PO6 PO3 PO2 PO1 PO0 Digital Input/Output Port Input/Output Timing Data fetch by 2-machine-cycle instructionData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instructionClock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation CircuitClock Generation Circuit Function and Operaion Processor clock control register PCCSEL MOV PCC, aFB3H PCC3 PCC2 PCC1 PCC0 PCCSystem clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry13 Example of Poor Resonator Connection Circuit 2/2 Use of Variable Minimum Instruction Execution Time Function CPU Clock SettingExample 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU ClockDifferences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1Peripheral Hardware Functions Clock Output Circuit Clock Output Circuit ConfigurationP22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Mode Register Clom ClomClock Output Procedure Examle of Remote Control ApplicationPeripheral Hardware Functions Basic Interval Timer Basic Interval Timer ConfigurationMPX BTM3 BTM2Basic Intercal Timer Mode Register BTM MOV BTM. aBTM3 BTMBasic Interval Timer Operation From the beginningExamples of Basic Interval Timer Applications MOV BTM,AIebt SEL MOVOperation-halted mode Wire serial I/O modePeripheral Hardware Functions Serial Interface Serial Interface FunctionsSBI mode serial bus interface mode Serial Interface ConfigurationSerial Interface Block Diagram FunctionsSerial operating mode register Csim Serial bus interface control register SbicShift register SIO SO latchIntcsi control circuit Register Functions Serial operating mode register CsimSerial clock control circuit Serial clock selection bit W Serial interface operating mode selection bit WCsie COI WUP CSIM3 CSIM1 Csim Signal from address comparator R CsieMOV CSIM, XA SET1 CsieCsie CSIM3 Csie CSIM1FE2H Cmdd Reld Cmdt ReltCommand trigger bit W Command detection flag RBus release detection flag R Acknowledge trigger bit WBusy enable bit R/W Acknowledge detection flag RCLK SIOBUSY/ACK Error detection See 5.5.6 8 Error detection for detailsSlave address register SVA Slave address detectionRegister setting Csie C0I WUP CSIM3 CSIM1 Csim5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System ConfigurationRemarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic29 3-Wire Serial I/O Mode Timing Communication operationSerial Clock Selection and Use in 3-Wire Serial I/O Mode SignalsSerial clock selection Relt CmdtData transfer order Start of transferWire serial I/O mode applications MOV XA, TdataMOV SIO, XA SCK SO/SB0MOV XA, Tdata SIO, XA IecsiMOV XA, Tdata XCH XA, SIO MOV RDATA, XASBI Mode Operation + VDDCPU SB0 SCK SB0 SCKAddress/command/data differentiation function Acknowledge signal ACK control functionBusy signal Busy control function SBI functionsSBI definition SB0 ACKSB0 C0 ACK Busy SB0 D0 ACK BusyBus release signal REL Command signal CMDSCK H SCK H SB0Address 37 Slave Selection by AddressCommand & data DataAcknowledge signal ACK SCK SB0 ACK100 Busy signal BUSY, ready signal ReadySCK SB0 ACK Busy 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105RELT, CMDT, Reld & Cmdd Operation Slave 106SIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK44 Ackt Operation 107When Acke is set after completion of transfer When Acke = 0 on completion of transferWhen Acke = 1 interval is short 108When ACK signal is output after 9th SCK clock interval 109SCK SB0 ACK Ackd SCK SB0 Bsye ACK110 Signals in SBI Mode SCK CmddSB0 ACK Ready SB0 Ready111 REL CMDPin configuration Pin Configuration DiagramUse of slave address register SVA Address match detection method113 114 ChapterPeripheral Hardware50 Command Transmission from Master Device to Slave 115116 51 Data Transmission from Master Device to Slave Device52 Data Transmission from Slave Device to Master Device 117Points to note concerning SBI mode 118Serial bus configuration SBI mode application119 Ii Communication procedure Description of commands Command types120 Iii Command formats ➀ Read command➁ WRITE, END and Stop commands 121MSM 122ACK Stop ➂ Status command 123Status MSB LSBReset command ➄ Chgmst command124 ChgmstIv Error occurrence Errors generated on the slave sideErrors generated on the master side 125Interrupt Functions 127 Interrupt Functions Interrupt Source Types and Vector Table Interrupt Request Source TypesVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0Interrupt request flag & interrupt enable flag Interrupt Request Flag Setting SignalExample EI IE0External interrupt input pin hardware 130INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise EliminationInterrupt master enable flag IME 132FB4H IM03 FB2HIST0 Interrupt Servicing Status Interrupt status flag133 YES Interrupt Functions Interrupt SequenceIME=1 Interrupt INTxxx generation 136 Interrupt enabling/disabling Interrupt Functions Interrupt ApplicationsEI Iecsi Example using INTBT, INT0 falling edge active, and Intcsi 138CLR1 IRQ0 ➄ Reti139 EI IE0➂ Intcsi Reti ➃ EI Iecsi Reti140 Pending interrupt executionINT0 Intcsi ➁ Reti Halt mode Stop modeStandby Function Standby Function Standby Mode Setting and Operation States Standby Mode Operation StatesStandby Function Standby Mode Reset Stop mode reset by Reset inputHalt mode reset by Reset input Halt mode reset by interrupt generation144 HaltStandby Function Operation After Standby Mode Reset IME =Reset Signal Acceptance Reset at Power-on147 State of Hardware after ResetOFF Architecture and Memory MAP 148Instruction SET Special Instructions Bit Manipulation InstructionsStack Instructions Example A0Base Correction Instructions Base correction at additionAddc Adds AddcOperation identifier and description Instruction SET Instruction SET and ITS OperationOperation description legend Description of machine cycle field Description of addressing area field symbols152 Movt XA, @PCXA AddsAddc XOR154 Instruction Group Instructions155 NOPDescription of operation code symbols Instruction SET Operation Code of Each InstructionBit manipulation addressing operation code Iebt Iecsi IE0 IE2Rorc Not Incs SET CLR SKT NotRET Rets Reti Push POP Halt Stop NOPInstruction SET Instruction Functions and Application Move InstructionsMOV A, #0BH MOV HL, #5FHMOV XA, 20H 160MOV XCH Loop XCH161 Table Reference Instructions Table data on that162 02FFHSee section Arithmetic and Logic Instructions163 Or A, @HL 164Rorc a 165Incs reg 166SKE reg, #n4 167Carry Flag Operation Instructions 168Bit Manipuration Instructions 169SKF mem. bit 170BR addr 171Subroutine Stack Control Instructions 172Push rp 173Interrupt Control Instructions 174Input/Output Instructions 175Halt 176177 178 Prom Writing Tools Language Processor179 Debugging Tools 180181 Development Tool ConfigurationIBM PC/AT 182 183 184 IrqcsPmgb Cmdd Port