NEC PD75P402 user manual ΜPD75402A I/O Map 2/2

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

Table 3-4 μPD75402A I/O Map (2/2)

Hardware Name (Symbol)

No. of Manipulatable

Bit

Address

Addressing

Manipula-

Remarks

tion

b3

b2

b1

b0

1 Bit

4 Bits

8 Bits

FE0H

Serial operation mode register (CSIM)

W

FE1H

* 1

mem. bit

0 must always be

CSIE

COI

WUP

0

written in bit 0.

FE2H

CMDD

RELD

CMDT

RELT

* 2

mem. bit

Bit manipulation

SBI control register (SBIC)

only is possible

FE3H

* 3

for all the bits.

BSYE

ACKD

ACKE

ACKT

FE4H

Serial I/O shift register (SIO)

R/W

FE6H

11000 must

Slave address register (SVA)

W

always be written

in the high-order

5 bits.

FE8H

Port mode register Group A (PMGA)

W

FECH

Port mode register Group B (PMGB)

W

FF0H

Port 0 (PORT 0)

R

R

FF1H

Port 1 (PORT 1)

R

R

Bits 3 and 1 are

fixed to 0.

FF2H

Port 2 (PORT 2)

R/W

R/W

fmem. bit

FF3H

Port 3 (PORT 3)

R/W

R/W

FF5H

Port 5 (PORT 5)

R/W

R/W

FF6H

Port 6 (PORT 6)

R/W

R/W

*1. Bits 3 and 1: W; bit 2: R.

2.Bits 3 and 2: R; bits 1 and 0: W.

3.Bits 3 and 1: R/W; bit 2: R; bit 0: W.

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