CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Wake-up function specification bit (W)

WUP

0IRQCSI set at end of every serial transfer in SBI mode mask state.

User only when functioning as a slave in SBI mode. IRQCSI is set only when the

1address received after bus release matches the slace address register data (wake-up status). SB0 is high impedance.

Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output after the BUSY release directive until the next fall of the serial clock (SCK). when setting WUP = 1, it is necessary to confirm that the SB0 pin has been driven high after BUSY is released before setting WUP = 1.

Signal from address comparator (R)

COI*

Clearing Conditions (COI = 0)

Setting Condition (COI = 1)

 

 

When slave address register (SVA) and

When slave address register (SVA) and shift

shift register data do not match.

register data match.

 

 

 

 

*A COI read is valid only before the start or after completion of a serial transfer. During a transfer an indeterminate value will be read.

Also, COI data written by an 8-bit manipulation instruction is ignored.

Serial interface operation enable/disable specification bit (W)

 

 

Shift Register

Serial Clock

IRQCSI Flag

SO/SB0 & SI Pins

 

 

Operation

Counter

 

 

 

 

 

 

 

 

 

 

 

1

Shift operation

Count operation

Settable

Function in each

CSIE

mode plus port 0

enabled

 

 

 

 

function

 

 

 

 

 

102

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NEC PD75402A, PD75P402 user manual Wake-up function specification bit W, 102