NEC PD75P402, PD75402A user manual State of Hardware after Reset, 147, Off

CHAPTER 8. RESET FUNCTION

Table 8-1 State of Hardware after Reset

		Hardware				RESET Input		RESET Input
					standby mode			during operation
Program counter (PC)				Low-order 3 bits of			Low-order 3 bits of
				program memory address			program memory address
				000H set in PC10 to PC8			000H set in PC10 to PC8
				and contents of address			and contents of address
				001H set in PC7 to PC0			001H set in PC7 to PC0
PSW	Carry flag (CY)					Retained			Undefined
	Skip flag (SK0 to SK2)				0			0
	Interrupt status flag (IST0)				0			0
Stack pointer (SP)						Undefined			Undefined
Data Memory (RAM)						Retained*			Undefined
General register (X, A, H, L)						Retained			Undefined
Basic interval timer			Counter (BT)			Undefined			Undefined
			Mode register (BTM)		0			0
Serial interface			Shift register (SIO)			Retained			Undefined
			Operation mode register (CSIM)		0			0
			SBI control register (SBIC)		0			0
			Slave address register (SVA)			Retained			Undefined
Clock generator,			Processor clock control register		0			0
clock output circuit			(PCC)
			Clock output mode register		0			0
			(CLOM)
Interrupt function			Interrupt request flag (IRQ×××)			Reset (0)			Reset (0)
			Interrupt enable flag (IE×××)		0			0
			Interrupt master enable flag (IME)		0			0
			INT0 mode register (IM0)		0			0
Digital input/output port			Output buffer			OFF			OFF
			Output latch			Clear (0)			Clear (0)
			I/O mode register (PMGA, PMGB)		0			0
			Pull-up resistor specification		0			0
			register (POGA)
Pin state			Pin state P00 to P03, P10, P12, P20			Input			Input
			to P23, P30 to P33, P60 to P63
			P50 to P53	•	On-chip pull-up resistor		•	On-chip pull-up resistor
					••••• High level			••••• High level
				•	Open-drain		•	Open-drain
					••••• High impedance			••••• High impedance

*The contents of data memory addresses 038H to 03DH are made undefined by RESET input.

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