NEC PD75402A, PD75P402 user manual Bus release detection flag R, 104

CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS

Bus release detection flag (R)

RELD

Clearing Conditions (RELD = 0) Setting Condition (RELD = 1)

➀When a transfer start instruction is executed

➁	When RESET is input	When the bus release signal (REL) is de-
➂	When CSIE = 0 (See Fig. 5-25)
		tected

4When SVA and SIO do not match when an address is received

Command detection flag (R)

CMDD

Clearing Conditions (CMDD = 0) Setting Condition (CMDD = 1)

➀When a transfer start instruction is executed

➁	When the bus release signal (REL) is	When the command signal (CMD) is de-
	detected
		tected
➂	When RESET is input

4When CSIE = 0 (See Fig. 5-25)

Acknowledge trigger bit (W)

ACKT

When ACKT is set after the end of a transfer, ACK is output in synchronization with the next SCK. After the ACK signal is output, ACKT is automatically cleared (0).

Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a transfer.

2.ACKT cannot be clearedby software.

3.When ACKT is set, ACKE should be reset to 0.

Acknowledge enable bit (R/W)

	0	Disables automatic output of the acknowledge signal (outpt by ACKT is possibel).
		When set before end of transfer	ACK is output is synchronization with the 9th
ACKE			SCK clock cycle.
	1
		When set after end of transfer	ACK is output in synchronization with SCK
			immediately after execution of the setting
			instruction.

Acknowledge detection flag (R)

ACKD

	Clearing Conditions (ACKD = 0)	Setting Condition (ACKD = 1)
➀	When a transfer is started
		When the acknowledge signal (ACK) is de-
➁	When RESET is input	tected (Synchronized with the rise of SCK)

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