Features of Architecture and Memory MAP | NEC PD75P402, PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

The μPD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below.

3.1DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES

3.1.1Data Memory Bank Configuration

The μPD75402A’s data memory space has a bank configuration. Addresses 000H to 03FH of Bank 0 are a data area as shown in Table 3-1 and are built in with a static RAM (64 × 4 bits). Addresses F80H to FFFH of Bank 15 are a peripheral hardware area and are built in with the input/output port, serial interface, etc. To address this data memory space of a 12-bit address, the low-order 8-bit address is specified directly or indirectly by an instruction. The high-order 4-bit address is determined by the memory bank (MB) to be accessed.

The μPD75402A is built in with only Memory bank 0 and 15 and does not require bank switching unlike other products of the 75X series. The memory bank to be accessed is determined by the addressing mode and the address to be specified (see Tables 3-1 and 3-2).

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NEC PD75P402, PD75402A user manual Features of Architecture and Memory MAP, Data Memory Bank Configuration

Contents

ΜPD75402A Page Major Revisions in This Version Remarks Content to be read carefullyInstruction Functions and Application Related Documentation Device Related Documents Development Tool Related DocumentsOther Related Documents Latest documents should be used for design purposes, etc Contents Basic Interval Timer Interrupt Control Circuit ConfigurationDigital INPUT/OUTPUT Ports Clock Generation Circuit Standby Mode Setting and Operation States Standby Mode ResetOperation After Standby Mode Reset Standby Mode Application Contents of Figures Fig. No Title Contents of Tables Table No Title ECR VCR GeneralFAX PPC General Outline of Functions For details, see Interrupt Functions Quality Grade General Ordering Information and Quality GradeOrdering Information VPP Block Diagram PORT0 PORT1 PORT2 PORT3 PORT5INT0 Interrupt INT2 Control PORT6 General PIN Configuration SCKSO/SB0 VPP NC Prom mode 2 44-Pin Plastic QFP 10mm Normal operating mode NC NC NC P50P01/SCK NC V SS NC P22/PCL A2 NC NC NC NC PIN Functions ΜPD75402A PIN Function List Port Pin List SCKSO/SB0 INT0 SCK SB0 PIN Functions Normal Operating Mode Port 0’s, 1’s Dual-Function Pins PCL ..... Port 2 Dual-Function Output 4 INT0 ..... Port 1 Dual-Function Input5 INT2 ..... Port 1 Dual-Function Input Reset Reset 7 X1, X2 Crystal PIN Functions Prom Mode CE Chip Enable ..... InputOE Output Enable ..... Input 1 A0 to A14 Address ..... Input PIN Functions PIN INPUT/OUTPUT Circuits Pin Input/output TypesRemarks a circle P22/PCL OUT IN/OUT Type F B Type M a P00, Reset PIN Functions Unused PIN Treatment Features of Architecture and Memory MAP Data Memory Bank Configuration FF0H Fffh FB0HFbfh Addressing Mode List @HL Bit direct addressing mem Data Memory Addressing ModesBit direct addressing mem.bit Bit register indirect addressing @HL Specific address bit manipulation addressing fmem. bit Stack addressing SUB Push POP RETPush HL POP Push HL Push XA RET Features of Architecture and Memory MAP MEMORY-MAPPED I/O Applicable Addressing Modes at Peripheral Hardware Operation ΜPD75402A I/O Map 1/2 ΜPD75402A I/O Map 2/2 PC1 PC0 Internal CPU FunctionsProgram Counter PC .... Bits Program Memory ROM .... ,920 Words × 8 Bits Program Memory Map Internal CPU Functions Data Memory RAM Data areaGeneral register area Stack area Peripheral hardware area General Register Configuration Internal CPU Functions General Register .... × 4 Bits Internal CPU Functions Accumulator Accumulators Internal CPU Functions Stack Pointer SP .... Bits Range of 020H to 03FHMOV SP, XA SP4 SP3 SP2 SP1 SP0 Data Saved to Stack Memory IST0 PSW Carry Flag Manipulation Instructions Internal CPU Functions Program Status Word PSW .... BitsCarry flag CY Interrupt Status Flag Indication Content SET1Skip flag SK2, SK1, SK0 Interrupt status flag IST0 Peripheral Hardware Functions PORT0 Digital Input/Output Port Types and Characteristics Csim Poga PO0PO1 INT2 INT0 Configuration of Port PO3 Configuration of Ports 2 Input/Output Mode Setting PM5 Pmgb Fech PM5 PM2 Pmgb Digital Input/Output Port Handling InstructionsPmga Bit handling instructions Digital Input/Output Port Operations Operations when input mode is setOperations when output mode is set Operations with Input/Output Port Handling Instructions Internal Pull-Up Resistor Specification for Each Port Internal Pull-up Resistors Fdch PO6 PO3 PO2 PO1 PO0 MOV POGA, XAPORT1 Digital Input/Output Port Input/Output Timing Data fetch by 2-machine-cycle instructionData latching by 1-machine-cycle instruction Data latching by 2-machine-cycle instruction Clock Generation Circuit Configuration Peripheral Hardware Functions Clock Generation Circuit Clock Generation Circuit Function and Operaion Processor clock control register PCCSEL MOV PCC, a FB3H PCC3 PCC2 PCC1 PCC0 PCC System clock oscillation circuit 12 System Clock Oscillation Circuit External Circuitry 13 Example of Poor Resonator Connection Circuit 2/2 Example CPU Clock SettingUse of Variable Minimum Instruction Execution Time Function 15 Change of Φ after Power-On Reset Maximum Time Required for Change of CPU Clock Differences Between μPD75402A and μPD75402 17 μPD75402 Processor Clock Control Register Format FB3H PCC3 PCC2 PCC1 P22/PCL CLOM3 CLOM1 CLOM0 Clom PORT2.2 Clock Output Circuit ConfigurationPeripheral Hardware Functions Clock Output Circuit Clock Output Mode Register Clom Clom Clock Output Procedure Examle of Remote Control Application Peripheral Hardware Functions Basic Interval Timer Basic Interval Timer ConfigurationMPX BTM3 BTM2 Basic Intercal Timer Mode Register BTM MOV BTM. aBTM3 BTM Basic Interval Timer Operation From the beginning Examples of Basic Interval Timer Applications MOV BTM,AIebt SEL MOV Operation-halted mode Wire serial I/O modePeripheral Hardware Functions Serial Interface Serial Interface Functions SBI mode serial bus interface mode Serial Interface Configuration Serial Interface Block Diagram Functions Serial operating mode register Csim Serial bus interface control register SbicShift register SIO SO latch Serial clock control circuit Register Functions Serial operating mode register CsimIntcsi control circuit Csie COI WUP CSIM3 CSIM1 Csim Serial interface operating mode selection bit WSerial clock selection bit W Signal from address comparator R Csie MOV CSIM, XA SET1 CsieCsie CSIM3 Csie CSIM1 FE2H Cmdd Reld Cmdt Relt Command trigger bit W Command detection flag RBus release detection flag R Acknowledge trigger bit W Busy enable bit R/W Acknowledge detection flag R BUSY/ACK SIOCLK Error detection See 5.5.6 8 Error detection for detailsSlave address register SVA Slave address detection Register setting Csie C0I WUP CSIM3 CSIM1 Csim 5 3-Wire Serial I/O Mode Operation 28 Example of 3-Wire Serial I/O System Configuration Remarks Figuer Apply to fXX = 4.19 MHz operation Shift register data do not match Register data match Command trigger bit FE2H Bsye Ackd Acke Ackt Cmdd Reld Cmdt Relt Sbic 29 3-Wire Serial I/O Mode Timing Communication operation Serial Clock Selection and Use in 3-Wire Serial I/O Mode SignalsSerial clock selection Relt Cmdt Data transfer order Start of transfer Wire serial I/O mode applications MOV XA, TdataMOV SIO, XA SCK SO/SB0 MOV XA, Tdata SIO, XA IecsiMOV XA, Tdata XCH XA, SIO MOV RDATA, XA SBI Mode Operation + VDDCPU SB0 SCK SB0 SCK Address/command/data differentiation function Acknowledge signal ACK control functionBusy signal Busy control function SBI functions SBI definition SB0 ACKSB0 C0 ACK Busy SB0 D0 ACK Busy Bus release signal REL Command signal CMDSCK H SCK H SB0 Address 37 Slave Selection by Address Command & data Data Acknowledge signal ACK SCK SB0 ACK SCK SB0 ACK Busy Busy signal BUSY, ready signal Ready100 101 102 103 104 Serial Clock Selection and Use in SBI Mode 105 RELT, CMDT, Reld & Cmdd Operation Slave 106SIO SCK SB0 Relt Cmdt Reld Cmdd SIO SCK 44 Ackt Operation 107 When Acke is set after completion of transfer When Acke = 0 on completion of transferWhen Acke = 1 interval is short 108 When ACK signal is output after 9th SCK clock interval 109SCK SB0 ACK Ackd SCK SB0 Bsye ACK 110 Signals in SBI Mode SCK CmddSB0 ACK Ready SB0 Ready 111 REL CMD Pin configuration Pin Configuration Diagram 113 Address match detection methodUse of slave address register SVA 114 ChapterPeripheral Hardware 50 Command Transmission from Master Device to Slave 115 116 51 Data Transmission from Master Device to Slave Device 52 Data Transmission from Slave Device to Master Device 117 Points to note concerning SBI mode 118 119 SBI mode applicationSerial bus configuration 120 Description of commands Command typesIi Communication procedure Iii Command formats ➀ Read command➁ WRITE, END and Stop commands 121 ACK Stop 122MSM ➂ Status command 123Status MSB LSB Reset command ➄ Chgmst command124 Chgmst Iv Error occurrence Errors generated on the slave sideErrors generated on the master side 125 Interrupt Functions 127 Interrupt Functions Interrupt Source Types and Vector Table Interrupt Request Source TypesVEN T1 GOT OBT VENT1 Gotobt VENT2 GOTO0 Interrupt request flag & interrupt enable flag Interrupt Request Flag Setting SignalExample EI IE0 External interrupt input pin hardware 130 INT0 Noise Elimination Circuit Input/Output Timing INT2 Input Noise Elimination Interrupt master enable flag IME 132FB4H IM03 FB2H 133 Interrupt status flagIST0 Interrupt Servicing Status IME=1 Interrupt Functions Interrupt SequenceYES Interrupt INTxxx generation 136 EI Iecsi Interrupt Functions Interrupt ApplicationsInterrupt enabling/disabling Example using INTBT, INT0 falling edge active, and Intcsi 138CLR1 IRQ0 ➄ Reti 139 EI IE0➂ Intcsi Reti ➃ EI Iecsi Reti INT0 Intcsi ➁ Reti Pending interrupt execution140 Standby Function Stop modeHalt mode Standby Function Standby Mode Setting and Operation States Standby Mode Operation States Standby Function Standby Mode Reset Stop mode reset by Reset inputHalt mode reset by Reset input Halt mode reset by interrupt generation 144 Halt Standby Function Operation After Standby Mode Reset IME = Reset Signal Acceptance Reset at Power-on OFF State of Hardware after Reset147 Architecture and Memory MAP 148 Instruction SET Special Instructions Bit Manipulation InstructionsStack Instructions Example A0 Base Correction Instructions Base correction at additionAddc Adds Addc Operation description legend Instruction SET Instruction SET and ITS OperationOperation identifier and description 152 Description of addressing area field symbolsDescription of machine cycle field Movt XA, @PCXA AddsAddc XOR 154 Instruction Group Instructions155 NOP Description of operation code symbols Instruction SET Operation Code of Each InstructionBit manipulation addressing operation code Iebt Iecsi IE0 IE2 Rorc Not Incs SET CLR SKT Not RET Rets Reti Push POP Halt Stop NOP Instruction SET Instruction Functions and Application Move InstructionsMOV A, #0BH MOV HL, #5FH MOV XA, 20H 160 161 Loop XCHMOV XCH Table Reference Instructions Table data on that162 02FFH 163 Arithmetic and Logic InstructionsSee section Or A, @HL 164 Rorc a 165 Incs reg 166 SKE reg, #n4 167 Carry Flag Operation Instructions 168 Bit Manipuration Instructions 169 SKF mem. bit 170 BR addr 171 Subroutine Stack Control Instructions 172 Push rp 173 Interrupt Control Instructions 174 Input/Output Instructions 175 Halt 176 177 178 179 Language ProcessorProm Writing Tools Debugging Tools 180 IBM PC/AT Development Tool Configuration181 182 183 184 IrqcsPmgb Cmdd Port