NEC PD75402A, PD75P402 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
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CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
The µ PD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below.
3.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
3.1.1 Data Memory Bank Configuration
The
µ PD75402A’s data memory space has a bank configuration. Addresses 000H to 03FH of Bank 0 are a data
area as shown in Table 3-1 and are built in with a static RAM (64 × 4 bits). Addresses F80H to FFFH of Bank 15 are
a peripheral hardware area and are built in with the input/output port, serial interface, etc. To address this data
memory space of a 12-bit address, the low-order 8-bit address is specified directly or indirectly by an instruction.
The high-order 4-bit address is determined by the memory bank (MB) to be accessed.
The
µ PD75402A is built in with only Memory bank 0 and 15 and does not require bank switching unlike other
products of the 75X series. The memory bank to be accessed is determined by the addressing mode and the address
to be specified (see Tables 3-1 and 3-2).