Sun Microsystems SME5224AUPA-400 manuals

56 pages341.67 Kb

DATASHEET
SME5224AUPA-400
UltraSPARC-II CPU Module
- 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION
  - Module Features Module Benets
- 2CPU D
  - UltraSPARC-II CPU
  - CPU Features CPU Benets
- 3D ATA B UFFER D
- E XTERNAL C ACHE D
- 4M ODULE COMPONENT O
  - Block Diagram
- 5S YSTEM I
- 7S IGNAL D
  - System Interface
    - 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25.
  - Clock Interface
  - 8JTAG/Debug Interface
  - Initialization Interface
  - Miscellaneous Signals
- 9UPAAND CPU CLOCKS
  - Module Clocks
  - System Clocks
  - System Clock Distribution
- 11E LECTRICAL C
  - Absolute Maximum Ratings
  - Recommended Operating Conditions
  - 12Module Power Consumption
  - DC Characteristics
  - 13UPA Data Bus SPICE Model
- 14U P AA CT
  - UPA_CLK Module Clocks
  - CPU_CLK Module Clock
  - Clock Buffers
  - Timing References
  - 15Timing Measurement Waveforms
    - Figure 5. Timing Measurement Waveforms
  - Propagation Delay, Output Hold Time Specications
- 16MECHANICAL SPECIFICATIONS
  - The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9.
  - Figure 7. CPU Module (Component Dimensions)
  - Figure 6. CPU Module Components
- 18T HERMAL S
  - Two Step Approach to Thermal Design
  - 19Thermal Denitions and Specications
  - 20Temperature Estimating and Measuring Methods
    - SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
- 22JTAGT
  - AC Characteristics - JTAG Timing
- 23JTAG(IEEE 1149.1) T
  - Figure 10. Voltage Waveforms - Setup and Hold Times
  - Figure 11. Voltage Waveforms - Propagation Delay Times
    - SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
- 24UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW)
- 25UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW)
- 26H ANDLING CPU M
- S TORAGEAND S HIPPING S
- 27ORDERING INFORMATION[1]
- D OCUMENT R EVISION H
- DATASHEET
- SME5224AUPA-400
29UltraSPARC-II CPU Module
- 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION
  - Module Features Module Benets
- 30CPU D
  - UltraSPARC-II CPU
  - CPU Features CPU Benets
- 31D ATA B UFFER D
- E XTERNAL C ACHE D
- 32M ODULE COMPONENT O
  - Block Diagram
- 33S YSTEM I
  - 7
- 35S IGNAL D
  - 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25.
  - System Interface
  - Clock Interface
  - 36JTAG/Debug Interface
  - Initialization Interface
  - Miscellaneous Signals
- 37UPAAND CPU CLOCKS
  - Module Clocks
  - System Clocks
  - System Clock Distribution
- 39E LECTRICAL C
  - Absolute Maximum Ratings
  - Recommended Operating Conditions
    - 12
    - SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
  - 40Module Power Consumption
  - DC Characteristics
  - 41UPA Data Bus SPICE Model
- 42U P AA CT
  - UPA_CLK Module Clocks
  - CPU_CLK Module Clock
  - Clock Buffers
  - Timing References
  - 43Timing Measurement Waveforms
    - Figure 5. Timing Measurement Waveforms
  - Propagation Delay, Output Hold Time Specications
- 44MECHANICAL SPECIFICATIONS
  - The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9.
  - Figure 7. CPU Module (Component Dimensions)
  - Figure 6. CPU Module Components
- 46T HERMAL S
  - Two Step Approach to Thermal Design
  - 47Thermal Denitions and Specications
  - 48Temperature Estimating and Measuring Methods
- 50JTAGT
  - AC Characteristics - JTAG Timing
- 51JTAG(IEEE 1149.1) T
  - Figure 10. Voltage Waveforms - Setup and Hold Times
  - Figure 11. Voltage Waveforms - Propagation Delay Times
    - 24
    - SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
- 52UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW)
- 53UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW)
- 54H ANDLING CPU M
- S TORAGEAND S HIPPING S
- 55ORDERING INFORMATION[1]
- D OCUMENT R EVISION H