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POST Code Reference Tables
These tables describe the POST codes and components of the POST process.
Post Code Range
Code | POST Routine Description |
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02h | Verify Real Mode |
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03h | Disable |
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04h | Get CPU type |
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06h | Initialize system hardware |
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08h | Initialize chipset with initial POST values |
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09h | Set IN POST flag |
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0Ah | Initialize CPU registers |
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0Bh | Enable CPU cache |
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0Ch | Initialize caches to initial POST values |
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0Eh | Initialize I/O component |
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| Code | Beeps | POST Routine Description |
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| 0Fh |
| Initialize the local bus IDE |
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| 10h |
| Initialize Power Management |
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| 11h |
| Load alternate registers with initial POST values |
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| 12h |
| Restore CPU control word during warm boot |
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| 13h |
| Initialize PCI Bus Mastering devices |
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| 14h |
| Initialize keyboard controller |
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| 16h | BIOS ROM checksum |
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| 17h |
| Initialize cache before memory autosize |
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| 18h |
| 8254 timer initialization |
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| 1Ah |
| 8237 DMA controller initialization |
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| 1Ch |
| Reset Programmable Interrupt Controller |
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| 20h | Test DRAM refresh |
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| 22h | Test 8742 Keyboard Controller |
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| 24h |
| Set ES segment register to 4 GB |
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| 26h |
| Enable A20 line |
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| 28h |
| Autosize DRAM |
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| 29h |
| Initialize POST Memory Manager |
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| 2Ah |
| Clear 512 KB base RAM |
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| 2Ch | RAM failure on address line xxxx* |
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| 2Eh | RAM failure on data bits xxxx* of low byte of memory bus |
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| 2Fh |
| Enable cache before system BIOS shadow |
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| 30h | RAM failure on data bits xxxx* of high byte of memory bus |
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| 32h |
| Test CPU |
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| 33h |
| Initialize Phoenix Dispatch Manager |
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| 36h |
| Warm start shut down |
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| 38h |
| Shadow system BIOS ROM |
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| 3Ah |
| Autosize cache |
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| 3Ch |
| Advanced configuration of chipset registers |
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122 | Chapter 4 |