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Item (NB Cont.) |
| Specification |
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Features | • | Hardware cursor up to 64x64 pixels in 2 bpp, full color AND/XOR mix, |
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| and full color |
| • Hardware icon up to 128x128 pixels in 2 bpp, with two colors, | |
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| transparent, and inverse transparent. AND/XOR mixing. Supports 2x2 |
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| icon magnification. |
| • | Virtual desktop support. |
| • Support for flat panel displays via VGA. | |
| VGA Output | |
| • Maximum resolutions supported by the VGA output for different refresh | |
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| rates are: |
| • 2048x1536 @85Hz (pixel clock at 388.5MHz) for 4:3 format | |
| • 2560x1440 @75Hz (pixel clock at 397.25MHz) for 16:9 format | |
| • 2456x1536 @60Hz (pixel clock at 320MHz) for 16:10 format | |
| • 1.3.10 Integrated LVDS Interface | |
| • Integrated | |
| • 805 Mbps/channel with 115 MHz pixel clock rate per link (230 MHz | |
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| maximum pixel clock). |
| • | |
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| Semiconductor, Texas Instruments, and THine. |
| • OpenLDI compliant excluding DC balancing. | |
| • Programmable internal spread spectrum controller for the signals. | |
| System Clocks | |
| • Support for an external clock chip to generate | |
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| and |
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| clocks, with clock input from an |
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| used (subject to characterization with actual RS880M and SB800- |
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| series devices). |
| Power Management Features | |
| • Single chip solution in 55nm, 1.1V CMOS technology. | |
| • Supports ACPI 2.0 for S0, S3, S4, and S5 states. | |
| • Full IAPC (Instantly Available PC) power management support. | |
| • Static and dynamic power management support (APM as well as ACPI) | |
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| with full VESA DPM and Energy Star compliance. |
| • The Chip Power Management Support logic supports four device power | |
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| states defined for the OnNow Architecture - On, Standby, Suspend, and |
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| Off. Each power state can be achieved by software control bits. |
| • Hardware controlled intelligent clock gating enables clocks only to | |
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| active functional blocks, and is completely transparent to software. |
| • Support for Cool'n'Quiet. via FID/VID change. | |
| • Support for AMD PowerNow!.. | |
| • Clocks to every major functional block are controlled by a unique | |
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| dynamic clock switching technique that is completely transparent to the |
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| software. By turning off the clock to the block that is idle or not used at |
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| that point, the power consumption can be significantly reduced during |
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| normal operation. |
| • Supports AMD | |
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| (enhanced with the ATI PowerShift. feature). |
| • Supports dynamic lane reduction for the PCIe graphics interface when | |
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| coupled with an |
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| Compliance |
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Chapter 1 | 19 |